Abstract: A digital pulse detector circuit having a selectable false alarm rate receives an analog input signal containing periodic correlation pulses in a background of noise. The input signal is sampled and digitized to produce a series of digital input samples which are taken for regular time slots within a series of time frames. Each of the digital input samples is summed with a previously stored digital summation sample to produce a new summation digital sample that replaces the summation sample read out of memory to produce the new summation sample. The new digital summation sample is compared to a threshold value to produce a signal confirmed signal to indicate detection of the correlation pulse. When a set number of summation steps are carried out for a particular time slot and the summation value for that time slot has not exceeded the threshold value, that time slot is reset to zero to eliminate accumulated noise.