Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.