Patents by Inventor Stuart P. Parkin

Stuart P. Parkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583212
    Abstract: A domain wall injector device uses electrical current passed across an interface between two magnetic regions whose magnetizations are aligned non-collinearly to create a domain wall or a series of domain walls in one of the magnetic regions. The method relies on a combination of innate fringing fields from the magnetic regions and the spin-transfer torque derived from the charge current. The device may be used to store data that are subsequently read out.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stuart P. Parkin, Timothy Phung, Aakash Pushp
  • Publication number: 20160056368
    Abstract: A domain wall injector device uses electrical current passed across an interface between two magnetic regions whose magnetizations are aligned non-collinearly to create a domain wall or a series of domain walls in one of the magnetic regions. The method relies on a combination of innate fringing fields from the magnetic regions and the spin-transfer torque derived from the charge current. The device may be used to store data that are subsequently read out.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: STUART P. PARKIN, Timothy Phung, Aakash Pushp
  • Patent number: 8896035
    Abstract: Disclosed is a metal oxide semiconductor field effect transistor (MOSFET) having phase transition material incorporated into one or more components and an associated method. The MOSFET can comprise an asymmetric gate electrode having a phase transition material section (e.g., a chromium or titanium-doped vanadium dioxide (VO2) section) above the drain-side of the channel region. Additionally or alternatively, the MOSFET can comprise source and drain contact landing pads comprising different phase transition materials (e.g., un-doped VO2 and chromium or titanium-doped VO2, respectively). In any case, the phase transition material(s) are pre-selected so as to be insulative when the MOSFET is in the OFF state and the voltage difference between the drain region and the source region (VDS) is high in order to minimize leakage current and so as to be conductive when the MOSFET is in the ON state and VDS is high in order to maintain drive current.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kota V. R. M. Murali, Edward J. Nowak, Stuart P. Parkin
  • Publication number: 20140110765
    Abstract: Disclosed is a metal oxide semiconductor field effect transistor (MOSFET) having phase transition material incorporated into one or more components and an associated method. The MOSFET can comprise an asymmetric gate electrode having a phase transition material section (e.g., a chromium or titanium-doped vanadium dioxide (VO2) section) above the drain-side of the channel region. Additionally or alternatively, the MOSFET can comprise source and drain contact landing pads comprising different phase transition materials (e.g., un-doped VO2 and chromium or titanium-doped VO2, respectively). In any case, the phase transition material(s) are pre-selected so as to be insulative when the MOSFET is in the OFF state and the voltage difference between the drain region and the source region (VDS) is high in order to minimize leakage current and so as to be conductive when the MOSFET is in the ON state and VDS is high in order to maintain drive current.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kota V. R. M. Murali, Edward J. Nowak, Stuart P. Parkin
  • Patent number: 7535069
    Abstract: A semiconductor device formed between a wordline and a bitline comprises a growth layer, an antiferromagnetic layer formed on the growth layer, a pinned layer formed on the antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, and a free layer formed on the tunnel barrier. The wordline and bitline are arranged substantially orthogonal to one another. The growth layer, in turn, comprises tantalum and has a thickness greater than about 75 Angstroms. Moreover, the pinned layer comprises one or more pinned ferromagnetic sublayers. The tunnel barrier comprises magnesium oxide. Finally, the free layer comprises two or more free ferromagnetic sublayers, each free ferromagnetic sublayer having a magnetic anisotropy axis that is oriented about 45 degrees from the wordline and bitline. The semiconductor device may comprise, for example, a magnetic tunnel junction for use in magnetoresistive random access memory (MRAM) circuitry.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Stephen L. Brown, Stuart P. Parkin, Daniel Worledge