Abstract: In some examples of both networks and methods, a data communication network includes a plurality of nodes. The nodes include a main node (MN) and at least one sub node (SNi=SN0, . . . SNX). Each node includes a node transceiver. The node transceiver is operable to perform data communication in accordance with a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus). A physical layer includes a cable segment (e.g., the cable segment of bus) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and a connector (e.g., 8P8C connector—though other connectors with multiple pairs of conductors can be used) at each end. A first pair of the conductors (e.g., connected to pin 4 and pin 5 of the 8P8C connector) implements the first network protocol between the nodes. One or more of the remaining pairs of the conductors provide supplemental power to the nodes 102.

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Abstract: In some examples of both networks and methods, a data communication network includes a plurality of nodes. The nodes include a main node (MN) and at least one sub node (SNi=SN0, . . . SNX). Each node includes a node transceiver. The node transceiver is operable to perform data communication in accordance with a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus). A physical layer includes a cable segment (e.g., the cable segment of bus) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and a connector (e.g., 8P8C connector—though other connectors with multiple pairs of conductors can be used) at each end. A first pair of the conductors (e.g., connected to pin 4 and pin 5 of the 8P8C connector) implements the first network protocol between the nodes. One or more of the remaining pairs of the conductors provide supplemental power to the nodes 102.

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Abstract: Disclosed herein are systems and techniques for adaptive use of multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver to couple to an upstream link of a bus of a communication system; and circuitry to couple to the upstream link of the bus and to a local power supply, wherein the circuitry is to switch from providing the local power supply to power the slave device to providing bus power supplied by the upstream link of the bus to power the slave device.

Abstract: Disclosed herein are systems and techniques for adaptive use of multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver to couple to an upstream link of a bus of a communication system; and circuitry to couple to the upstream link of the bus and to a local power supply, wherein the circuitry is to switch from providing the local power supply to power the slave device to providing bus power supplied by the upstream link of the bus to power the slave device.

Abstract: In an example embodiment, a power switching circuit of an automobile audio bus (A2B) chip is provided in a bi-directional, multi-node two-wire conductor system that includes a plurality of A2B chips interconnected on a twisted wire pair bus (A2B bus), with at least one A2B chip functioning as a master and the remaining A2B chips functioning as slaves. The power switching circuit of the A2B chip powers up a next downstream A2B chip in the A2B bus sequentially according to a power switching procedure, and the power switching circuit is configured to detect faults in the A2B bus before, during, and after the power switching procedure. Each A2B chip enables power to the next downstream A2B chip without risk of damage to any components in the system due to line faults on the downstream A2B bus, or collapse of the power supply at the local A2B chip.

Abstract: In an example embodiment, a power switching circuit of an automobile audio bus (A2B) chip is provided in a bi-directional, multi-node two-wire conductor system that includes a plurality of A2B chips interconnected on a twisted wire pair bus (A2B bus), with at least one A2B chip functioning as a master and the remaining A2B chips functioning as slaves. The power switching circuit of the A2B chip powers up a next downstream A2B chip in the A2B bus sequentially according to a power switching procedure, and the power switching circuit is configured to detect faults in the A2B bus before, during, and after the power switching procedure. Each A2B chip enables power to the next downstream A2B chip without risk of damage to any components in the system due to line faults on the downstream A2B bus, or collapse of the power supply at the local A2B chip.

Abstract: A multi-voltage biasing system with over voltage protection has an amplifier with a stage including at least one output device and one cascode protection device having a predetermined maximum recommended voltage; a biasing network is selectively responsive to a plurality of different supply voltages at least one of which is higher than the maximum recommended voltage for providing to the stage a bias voltage to operate the cascode device and output device below their maximum recommended voltages.

Abstract: A system and method for determining the true electrical characteristics of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristics. An updateable database is populated with application circuit information and a software routine is responsive to the measured electrical characteristic and configured to adjust the electrical characteristics measured by the codec based on the application circuit information in the database.

Abstract: An identification system and method for recognizing a device as one of a plurality of different types of devices connected to at least one terminal of an information handling system includes supplying a test signal to a device in a test mode; measuring an electrical characteristic of the device in response to the test signal being applied to the device in the test mode; and matching a representation of the electrical characteristic of the device with representations of the electrical characteristics of the plurality of devices for recognizing the device connected to the terminal as one of the plurality of different devices.

Abstract: A system for verifying the identification of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristic. An updateable database is populated with the electrical characteristic of at least one device whose electrical characteristic was measured by the codec but not correctly identified by the codec and a software routine is responsive to the measured electrical characteristic and configured to adjust the codec's identification of the device based on the electrical characteristic stored in the database to correctly identify the device.

Abstract: A system for verifying the identification of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristic. An updateable database is populated with the electrical characteristic of at least one device whose electrical characteristic was measured by the codec but not correctly identified by the codec and a software routine is responsive to the measured electrical characteristic and configured to adjust the codec's identification of the device based on the electrical characteristic stored in the database to correctly identify the device.

Abstract: A system and method for determining the true electrical characteristics of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristics. An updateable database is populated with application circuit information and a software routine is responsive to the measured electrical characteristic and configured to adjust the electrical characteristics measured by the codec based on the application circuit information in the database.

Abstract: A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.

Abstract: An output driver in an integrated circuit includes a driver circuit operable by a power supply voltage and coupled to an output pad, and a driver power conditioner configured to generate a fractional pad voltage in response to a voltage on the output pad and to provide the fractional pad voltage to at least one transistor of the driver circuit as a protected supply voltage in response to an absence of the power supply voltage.

Abstract: A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.

Abstract: A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.

Abstract: An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

Abstract: A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.