Abstract: A user-mode device driver architecture is provided by the subject invention. The architecture includes a reflector, a driver manager and a host process which hosts and isolates one or more user-mode device driver(s). The user-mode device driver runs in the user-mode (UM) environment and has access to various UM services. The reflector resides in “kernel memory” (e.g., memory/resource(s) available to operating system) while the driver manager, host process and user mode device driver(s) are located in user space (e.g., memory/resource(s) available to user application(s)). The reflector provides a secure, stable communication path for application(s), the host process and/or user-mode device driver(s) to communicate with the operating system.

Abstract: The present invention leverages high-frequency interrupts and/or low priority threads to accurately determine which computing resources are available. This provides a computing asset (CPUs and/or software applications) with a means to accurately compensate for resource utilization in order to increase its performance. By utilizing the present invention, the computing asset can optimize its performance in a real-time, self-tuning manner. In one instance of the present invention, high intensity, low priority threads are initiated on available CPUs (logical and/or physical) to effectively replace a CPU's idle time with the low priority thread. This thread generally constitutes a computationally-intensive and/or a memory-intensive thread which permits a highly accurate performance measurement to be obtained for available CPU resources.

Abstract: A method and apparatus for providing access to a banked peripheral memory via a contiguous linear address space. The present invention provides a linear address space having a present region that is mapped to a host memory region of a computer system. The present invention further provides a relocatable selector that provides access to a portion of the linear address space. Accessing programs exchange data with the banked peripheral memory via the relocatable linear address space. When an accessing program references an address of the relocatable address base that is not mapped to the present region, the relocatable linear address space is positioned so that the referenced address maps to the present region. Additionally, a bank of the peripheral memory that corresponds to the referenced address is also mapped into the host memory region so as to enable the accessing program to exchange data with the banked peripheral memory via the relocatable linear address space.

Abstract: The stack pointer register in a computer is made available for general purpose use by programs executing at lower privilege levels than interrupt handlers. A set of instructions in such programs, excluding stack operations, stores data other than the stack pointer, such as operands, and the like, in the stack pointer register. When switching execution to an interrupt handler on an interrupt, return address data for the currently executing program is pushed onto a stack at the interrupt handler's privilege level. Thus, storing other data in the stack pointer register does not result in stack corruption. Also, these instructions can store data in a scratch portion of a stack segment beyond the current stack pointer.

Abstract: A method for storing a sequence consisting of a repeated data pattern of three bytes to a memory in double word increments aligned with double word boundaries. A register is loaded with the first four bytes of the sequence. The contents of the register are then repeatedly stored to consecutive locations of the memory. Between each storing of the register's contents, the contents are updated to the next four bytes of the sequence by shifting the second through fourth bytes to the first through third bytes and also moving the second byte to the fourth byte. When the beginning address where the sequence is to be stored in memory is not aligned with a double word boundary, the initial bytes of the sequence up to the double word boundary are stored and the contents of the register updated to the next four bytes of the sequence.

Abstract: A method for fetching data in the form of a group of source bits (bytes, words, etc.) from computer memory and providing successive portions of the group to a computer process. An indicator such as a bit string is loaded into one location of a register and the group of source bits is loaded into another location in the register. The contents of the register are then rotated to move successive portions of the group into a register location where the portions can be accessed for a process. Tracking the processing of the successive portions of the bit group is handled efficiently in a loop through monitoring of the indicator, which "walks" through the register concurrently with movement of the successive portions of the source bit group. When the indicator bit has returned to its initial register location, the processing of the group of source bits is complete.

Abstract: The outputting of transparent text to a video display is improved by decreasing the time it takes to output the text. The time savings are realized by eliminating the "OUT" instruction that is particularly time consuming. This invention is especially well-adapted for use with a video graphics array (VGA) type video adapter.