Abstract: A stacked field effect transistor (FET) device. The device includes an opening in a shallow trench isolation (STI) region on a substrate. The device also includes an epitaxy region located on the substrate at a bottom portion of STI region in the opening. The device further includes a substrate contact that directly contacts the epitaxy region.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.

Abstract: A semiconductor device is provided. The semiconductor device includes an interlayer dielectric layer; and a plurality of metal contacts formed in the interlayer dielectric layer. The plurality of metal contacts include a plurality of shallow metal contacts having a first depth, and a plurality of deep metal contacts having a second depth that is greater than the first depth, wherein a first one of the shallow metal contacts overlaps and directly contacts a first one of the deep metal contacts, and wherein the plurality of metal contacts have an equal spacing therebetween.

Abstract: A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form transistors on a substrate. The fabrication operations include forming a sacrificial metal gate and forming a shared non-sacrificial metal gate. The sacrificial metal gate is recessed to form a sacrificial metal gate, and the shared non-sacrificial metal gate is recessed to form a recessed shared non-sacrificial metal gate. A pattern is formed over the sacrificial metal gate and the recessed shared non-sacrificial metal gate. The pattern defines a single diffusion break footprint over a top surface of the sacrificial metal gate, along with a gate-cut footprint over a central region of a top surface of the recessed shared non-sacrificial metal gate.

Abstract: A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

Abstract: Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

Abstract: A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Abstract: A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

Abstract: Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.