Abstract: A permuted interleaver/deinterleaver system for interleaving the bits of a digital communications system such that bursts of error bits are separated for more effective communications. The interleaver/deinterleaver system includes an interleaver and deinterleaver having a number of permuted rows of shift registers. The arrangement of the shift registers in the interleaver and deinterleaver can be determined by a permute number calculated in accordance with a specific communications implementation. As bits are input into the shift register of the interleaver, bits are output from the interleaver in order to establish a sequence of permuted data bits. A rotating switching mechanism systematically selects output bits from the shift register of the interleaver and applies the bits to a channel modulator/demodulator. The deinterleaver accepts the bits from the channel and restores the original bit order.

Abstract: A technique for producing detection and synchronization signals with respect to a received pseudo-random (PN) signal, with optimum signal-to-noise performance and reduced complexity and cost of hardware. Correlation of the received signal with early and late reference signals is performed in such a way that multiplication hardware is time-shared to produce an early/late sum signal for use in signal detection, and an early/late difference signal for use in synchronization, but without the degradation of performance usually resulting from time-sharing of components. In one basic form of the invention, the received signal is multiplied by one of the local reference signals, and the resulting product is demultiplexed over two alternate paths for computation of the required sum and difference signals.