Abstract: Methods and system are provided for remote management of an IHS (Information Handling System). A keypair is generated by a client management application using operating system capabilities of the IHS. The client management application, as a privileged operating system user, writes a public key of the keypair to UEFI (Unified Extensible Firmware Interface) variables stored within a secured data storage device of the IHS. A BIOS of the IHS retrieves the public key from the UEFI variables and uses it to encrypt a remote management secret. The BIOS writes the encrypted secret back to the UEFI variables. The client management application uses the keypair to recover the remote management secret from the encrypted secret that was written to the UEFI variables by the BIOS. The secret is used to establish a secure remote management session between the client management application and a remote access controller of the IHS.

Abstract: Methods and system are provided for remote management of an IHS (Information Handling System). A keypair is generated by a client management application using operating system capabilities of the IHS. The client management application, as a privileged operating system user, writes a public key of the keypair to UEFI (Unified Extensible Firmware Interface) variables stored within a secured data storage device of the IHS. A BIOS of the IHS retrieves the public key from the UEFI variables and uses it to encrypt a remote management secret. The BIOS writes the encrypted secret back to the UEFI variables. The client management application uses the keypair to recover the remote management secret from the encrypted secret that was written to the UEFI variables by the BIOS. The secret is used to establish a secure remote management session between the client management application and a remote access controller of the IHS.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: An adaptive card-sensitive bus slot system and method. The method and system include a substantially universal bus slot structure. In one embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key. In another embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key piston. In another embodiment, a data processing system includes the adaptive card-sensitive bus slot system.

Abstract: An adaptive card-sensitive bus slot system and method. The method and system include a substantially universal bus slot structure. In one embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key. In another embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key piston. In another embodiment, a data processing system includes the adaptive cardsensitive bus slot system.

Abstract: An adaptive card-sensitive bus slot system and method. The method and system include a substantially universal bus slot structure. In one embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key. In another embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key piston. In another embodiment, a data processing system includes the adaptive card-sensitive bus slot system.

Abstract: A filter circuit for filtering bus accesses from a computer bus (such as e.g. a bus conforming to the PCI standard) to a group of devices operably coupled to the computer bus in a computer system. The filter circuit operates in a filter mode and a non filter mode. In the non filter mode, the filter circuit allows bus accesses to pass from the computer bus to the group. In the filter mode, the filter circuit blocks bus accesses from passing to the group. Upon determining that a bus access is an allowable bus access, the filter circuit initiates a retry request to signal the bus master that initiated the allowable bus access to reinitiate the bus access, wherein the filter circuit allows the allowable bus access to pass to the group. The filter circuit includes a switch circuit and a control circuit that places the switch circuit in the conductive and non conductive switch states to allow bus accesses to pass and to be blocked from passing to the group, respectively.

Abstract: It has been discovered that providing a computer system with a hot pluggable power supply as well as a disconnectable resistive load allows a second power supply to be brought on-line while operating within the proper voltage range and then disconnecting the resistive load from the power supply so as to conserve energy and lower the operating temperature of the computer system. Such a system also conserves energy by reducing the size of the fan that the computer system requires. Such a system also allows for a the use of larger test resistor thus providing a more accurate load test. Such a system also allows for saving space as one test circuit can be used for both power supplies. Such a system also allows for a reduced capacity power supply as the power supply does not have to continuously supply power to the resistive test load.

Abstract: The present invention provides a computer system which electronically and automatically detects the maximum rated operating frequency of a microprocessor installed in the computer system. The present invention also electronically and automatically detects, selects and generates a "common" external/internal operating clock frequency in a multiprocessor system when more than one microprocessor is installed in the computer system. More particularly, a computer system is disclosed which includes at least one microprocessor and a main memory coupled to each microprocessor. Each microprocessor includes an electronic stamp with a value of a maximum rated operating frequency for the microprocessor written therein. The computer system includes a clock generating section for electronically detecting the value of the maximum rated operating frequency of the each microprocessor and for selecting and generating an operating frequency for the computer system.

Abstract: The present application describes a tuned guard circuit device and method for controlling impedance levels of transmission lines on a printed circuit board having at least one ground plane and at least two circuit components coupled by a conductive transmission line. The guard circuit device of the present invention includes two etched conducting guard bands on the printed circuit board disposed on opposite sides of a selected transmission line and affixed in a spaced parallel relation to the transmission line. The guard bands are of substantially constant width and substantially constant distance from the ground plane and have substantially the same length as the transmission line, and each guard band has a first and a second terminal end. Also included is a capacitor connected to the ground plane and connected at each of the first and second terminal ends of each guard band wherein the guard bands are connected to ground through the capacitors.