Abstract: Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics that interfere with AM radio reception. This interference has precluded wide spread acceptance of class D amplifiers in products that include an AM radio. The amplifier described here uses a a harmonic avoidance modulator when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or the intermediate (IF) frequency thereof.

Abstract: Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics that interfere with AM radio reception. This interference has precluded wide spread acceptance of class D amplifiers in products that include an AM radio. The amplifier described here uses a a harmonic avoidance modulator when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or the intermediate (IF) frequency thereof.

Abstract: A circuit for avoiding AM radio interference in a class D amplifier includes comparing means that compares the frequency of an AM signal to one or more reference signals. The comparing means generates comparator signals indicative of whether the first signal is greater than, less than or equal to the reference signals. A frequency divisor signal that represents a frequency divisor number is issued dependent at least in part upon the comparator signals. Dividing means generate an oscillator signal for the class D amplifier that has a frequency derived by dividing the frequency of the AM signal by the frequency divisor number.

Abstract: Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment uses a harmonic avoidance modulator. A second embodiment uses two or more oscillators and tests for the least distorted output signal. A third embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified.

Abstract: An output stage for a class D amplifier reduces distortion and EMI, and greatly improves the efficiency. The output stage employs a combination of techniques including a soft switching network, multiple output inductors and beads to achieve, a high power full range class D amplifier that is complies with all FCC and CE specifications with greater than 90% efficiency at ⅓ power.

Abstract: The frequency spectrum of variable frequency class D modulator interferes with RF signals in the AM bandwidth. Here several techniques solve the problem including an amplifier that synchronizes an external clock input the summing node of the integrator, an amplifier that gates an external clock to the modulator using a transmission gate that responds to the AM frequency, and an amplifier that adjusts its own hysteresis to provide a clock that does not interfere with AM input signals.

Abstract: A high Q low pass filter removes the carrier from a Class D amplifier. Speaker impedance varies with frequency, and it is desirable for to drive 2, 4 and 8 ohm speakers. The bandwidth feedback compensation network 800 adds a pole-zero combination to the feedback loop to reduce the Q of the low pass filter and to maintain the bandwidth of the amplifier.

Abstract: The low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in the half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is further designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.

Abstract: The OCL 200 receives two logic signals: the first, OC upper FET, is high when an over current condition exists in the upper FET 22; the second, OC lower FET, is high when an over current condition exists in the lower FET 24. When the over current condition is in FET 22, PMOS 212 turns on and injects current into the summing junction of the integrator 10 through Rcl. The net effect is turn off the upper FET 22 and turn on the lower FET 24. This reduces the current in FET 22. As far as amplifier 100 is concerned, the net effect is gain compression. Since upper FET 22 is on less and the lower FET 24 is on more, the gain of the audio signal is reduced. When the over current condition is in FET 24, NMOS 213 turns on and pulls current out of the summing junction, turns the lower FET 24 off, and turns the upper FET 22 on. The net effect is to reduce the current in the lower FET. At audio frequencies, the gain is reduced.

Abstract: Load-monitoring feedback is used to maintain the slew rate of a line driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics of the signal line, which may vary over a specified range of component values. In a first embodiment, slew rate control is effected by increasing or decreasing the amount of charge on a reference capacitor and thereby the drive current to an output driver FET, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to termination of a prescribed (one-shot established) time window.

Abstract: A class D modulator 100 is self oscillating. It includes an input stage 110, an operational amplifier 120, an integrator 130 and a pulse width modulator 140. A start-up generator 22 generates signals ENABLE and MUTE. The MUTE signal is connected to the input stage 110 to prevent any unwanted, initial sound. The ENABLE signal connects a start-up voltage source to the integrator 130 to set the initial voltage for integration. The ENABLE signal is coupled to a dead time control circuit 16 which controls the operation of the output power transistors 42, 44 to assure that the low side power transistor 44 is turned on before the high side transistor 42.

Abstract: A sensing circuit 100 includes two resistors 11 and 12, two pnp transistors 13 and 14, and a current mirror 15 and 16. Resistors 11 and 12 convert the high voltages present in the bridge into a proportional current. The current mirror, mosfets 15 and 16, compares I.sub.1 and I.sub.2. If I.sub.2 is greater than I.sub.1 the voltage at point A is high. Otherwise this voltage is low. Resistor 12 is chosen smaller than 11 so that under normal operation, when FET 22 turns on, I.sub.2 is greater than I.sub.1 and the voltage at point A is high. During an overcurrent event, the drop across the FET 22, Von, is so great that I.sub.2 is less than I.sub.1 and the voltage a point A stays low.

Abstract: A class D amplifier 100 has an integrator 10, a comparator 12, and a frequency compensation and gain control (FCGC) circuit 40. The FCGC circuit 40 senses the output and reduces the gain in order to keep the sampling frequency high enough to avoid audio artifacts.