Abstract: A fast operating, combined packet and circuit switch. The switch includes a number of units which are distributed locally and which are mutually connected by means of physical links. In a packet-switched network, which is comprised of packet handlers and the links, each connected unit affects at least one control-time-slot. In this way, each unit is able to operate the circuit switch so as, for instance, to establish and release circuit-switched connections, in response to control commands transmitted on the packet-switched network. As a result of the packet switch, the whole of the switch can be configured at a cold start and during operation, therewith satisfying the individual bandwidth requirement of each connected unit.

Abstract: The invention relates to a method and a device for testing and supervising majority votes in a multiplane digital time selector with essentially identical equipment in each of at least three planes (A,B,C) working in parallel. An incoming data flow is distributed to the planes and is allowed to pass through the equipment in each of them and gives rise to outgoing data streams. These outgoing data streams are compared to each other and a majority voted outgoing data flow based upon the comparison is delivered from the unit. An error is periodically introduced in accordance with a predetermined pattern in the three planes and the data streams arriving at the majority vote and the majority voted data flow are compared. If an error is then found in any of the data streams an alarm is emitted.

Abstract: A galvanic switch for electrically making or breaking one cross-point among a plurality of cross-points in a three-dimensional switching matrix. The switch includes electrical contact lines, first links which extend perpendicular to the contact lines, and second links which extend perpendicular to both the contact lines and the first links. At each cross-point, there is located a contact element in the form of a spherical element for making and breaking the electric contact respectively. The contact elements either make or break the cross-point depending on whether the coupling element is conductive or non-conductive, and are maneuvered by maneuvering elements.

Abstract: The present invention relates to a function unit for electronic equipment, comprising a center plane with contact pins mounted thereon, distribution boards which can be inserted at right angles to the center plane, from both sides thereof, and circuit boards capable of being connected in plane-parallel with the distribution boards. In accordance with the invention, the center plane is provided with groups of contact pins disposed in rows and columns, the pins being isolated electrically from the center plane and extending therethrough. The contact pins are disposed along one whole edge margin of the center plane in a terminal field which can be reached from one side of the center plane. The distribution boards along the edge margin which faces towards the center plane are provided with a contact device adapted to mate with the contact pins, whereas the opposing edge margin is provided with one or more contact devices for connection of a coinciding number of circuit boards.

Abstract: A matrix crosspoint switching device makes, breaks, or switches contact between a plurality of first conductor pairs and a plurality of second conductor pairs. The device includes a connection block which includes a plurality of cavities containing crosspoints of the pluralities of conductor pairs. Pairs of conductive and nonconductive roller elements are also contained in the cavities for selectively making, breaking, or switching contacts between the conductor pair crosspoints.

Abstract: Synchronization apparatus in a telecommunication system of the TDM type in which information is transmitted in assigned time slots, in simplex data transmission between a plurality of equal transmitter/receiver modules (A-N) connected to a common bus. The bus is divided into three sections, all transmitters (S) being successively connected to the first section (B1) and all receivers (R) being connected to the final section (B3) in the same order as the transmitters. The time delay between transmitters and bus is the same for all transmitters and constitutes a fixed value, whereby the total delay on the first section of the bus is determined by the number of transmitters connected. The same condition applies to the receivers so that the delay on the final section (B3) of the bus also is fixed value.

Abstract: The invention relates to a method and apparatus in duplex transmission of digital information between subscribers connected to terminals associated with each other in a telecommunication network of the time multiplex type in which information is transmitted in the form of binary words in specially assigned time slots, of carrying out with the aid of parity check, during traffic in progress, through-connection testing for checking that a correct connection has been set up after a switching path has been established. The through-connection check is started and detected in the same station (terminal). After detected correct parity, which is done with the aid of a parity check means (M1) and a comparison circuit (OR), there is generated a parity bit with intentional incorrect polarity for sending on the line towards the next station. Generation of desired parity is done with the aid of an apparatus including a local processor (MP), a control memory (CM), a counter (TR) and said comparison circuit.

Abstract: A digital concentrator includes line circuit modules (3,4) and provides time-division multiplex (TMD) channel set-ups between a bus (5), connected to all modules, and PCM links (1), each going from its own module, the number of links being less than the number of modules, as well as between groups of subscriber lines (2), connected to the modules, and the bus (5), and between the subscriber line group and the link being connected to the same module (4). The bus must always be used for a set-up to an arbitrary link from a subscriber line, the line circuit module (3) of which is solely connected to the bus (5). In order to avoid congestion on the bus as far as possible the bus is only used for a set-up to an arbitrary link from a subscriber line, the module (4) of which is connected to the bus (5) and to one of the links (1), solely if a given number of the TDM channels of the link associated with this module are already busy.

Abstract: The invention relates to a method for regulating the phase position of a controlled signal in relation to the phase position of a reference signal in a telecommunication system, and an arrangement for carrying out the method. A reference signal (C2) is delayed in a delay circuit (DL1) and the delayed reference signal (C2) is delayed in a delay circuit (DL1) and the delayed reference signal (D1) is compared with a controlled signal (C1) in a first comparison circuit (FF1) which produces a first comparison signal (Q1) at a high or a low level in dependence on the phase difference between the delayed reference signal (D1) and the controlled signal (C1). The controlled signal (C1) is delayed in a delay circuit (DL2) and the delayed controlled signal (D2) is compared in a second comparison circuit (FF2) with the reference signal (C2).

Abstract: The invention concerns an arrangement for transmission of certain clock signals in a series of clock signals by means of signals of lower frequency compared to the frequency of said series of clock signals. From said signals of lower frequency well-defined pulses are extracted for controlling logic equipment located distantly from the clock pulse source. The arrangement includes at the sender side a clock pulse generator producing said series of clock signals, a counter which is stepped by said series of clock pulses and produces at least two pulse series phase displaced with respect to each other where the length of the pulses of said pulse series is a multiple of the length of the pulses of the first mentioned clock pulse series. The phase displacement between said at least two pulse series corresponds to half the length of the pulses of said clock pulse series. The frequency of said at least two pulse series is lower than the frequency of said clock pulse series.