Abstract: Reinforcement learning (RL) based chip design optimization using trained graph convolutional networks (GCN) may include generating an elaborated circuit design based on a high-level circuit design and permuton values for permutons of the high-level circuit design, inferring metrics of the elaborated circuit design with a machine-learning (ML) engine, evaluating the inferred metrics and the permuton values of the elaborated circuit design and revising the permuton values based the evaluation to optimize the inferred metrics, using a RL engine, and revising the elaborated circuit design based on the revised permuton values. An apparatus may include a ML engine that infers metrics of an elaborated circuit design, and a RL engine that determines a correlation between the inferred metrics and permuton values of the elaborated circuit design and revises the permuton values based on the inferred metrics and the correlation to optimize the inferred metrics with respect to optimization criterion.

Abstract: A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.

Abstract: A method includes receiving a crash signature and a crash configuration. The crash signature is generated in response to a software crash in a software application caused by the crash configuration. The method also includes applying a first machine learning model to determine a reference of a plurality of references that is closest to the crash signature and the crash configuration. The reference includes a reference crash signature and a reference configuration. The reference crash signature and the reference configuration are generated by a proxy crash to the software crash.