Patents by Inventor Su Bin BAE
Su Bin BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210384287Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.Type: ApplicationFiled: August 19, 2021Publication date: December 9, 2021Inventors: Sang Gab KIM, Hyun Min CHO, Tae Sung KIM, Yu-Gwang JEONG, Su Bin BAE, Jin Seock KIM, Sang Gyun KIM, Hyo Min KO, Kil Won CHO, Hansol LEE
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Patent number: 11183518Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.Type: GrantFiled: August 7, 2020Date of Patent: November 23, 2021Assignee: Samsung Display Co., Ltd.Inventors: Yu-Gwang Jeong, Hyun Min Cho, Su Bin Bae, Shin Il Choi, Sang Gab Kim
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Patent number: 11127724Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.Type: GrantFiled: November 21, 2019Date of Patent: September 21, 2021Assignee: Samsung Display Co., Ltd.Inventors: Su Bin Bae, Yu Gwang Jeong, Shin Il Choi, Joon Geol Lee, Sang Gab Kim
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Patent number: 11127807Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.Type: GrantFiled: July 24, 2019Date of Patent: September 21, 2021Inventors: Sang Gab Kim, Hyun Min Cho, Tae Sung Kim, Yu-Gwang Jeong, Su Bin Bae, Jin Seock Kim, Sang Gyun Kim, Hyo Min Ko, Kil Won Cho, Hansol Lee
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Patent number: 11101336Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.Type: GrantFiled: January 29, 2019Date of Patent: August 24, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yu-Gwang Jeong, Su Bin Bae, Joon Geol Lee, Sang Gab Kim, Shin Il Choi
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Publication number: 20210217738Abstract: A display device includes a substrate and a display element layer on the substrate. The display element layer includes: first and second electrodes extending along a first direction and spaced apart from each other in a second direction; and light emitting elements electrically connected to the first and second electrodes. The first electrode has a first convex portion convex toward the second electrode and a first concave portion concave in a direction away from the second electrode, and the second electrode has a second convex portion convex toward the first electrode and a second concave portion concave in a direction away from the first electrode. The light emitting elements includes a first and second light emitting elements, respectively close to the first concave portion and the second concave portion based on an imaginary extension line extending in the first direction between the first electrode and the second electrode.Type: ApplicationFiled: November 10, 2020Publication date: July 15, 2021Inventors: Su Bin BAE, Seon Il KIM, Sung Won CHO, Yun Jong YEO, Yu Gwang JEONG
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Publication number: 20210132424Abstract: A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 ? to about 300 ?, and a thickness of the main conductive layer is in a range of about 1,000 ? to about 20,000 ?.Type: ApplicationFiled: June 18, 2020Publication date: May 6, 2021Applicant: Samsung Display Co., LTD.Inventors: Seon-Il KIM, Sung Won CHO, Sang Gab KIM, Su Bin BAE, Yu-Gwang JEONG, Dae Won CHOI
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Publication number: 20200365620Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.Type: ApplicationFiled: August 7, 2020Publication date: November 19, 2020Inventors: Yu-Gwang JEONG, Hyun Min Cho, Su Bin Bae, Shin Il Choi, Sang Gab Kim
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Patent number: 10741589Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.Type: GrantFiled: December 10, 2018Date of Patent: August 11, 2020Assignee: Samsung Display Co., Ltd.Inventors: Yu-Gwang Jeong, Hyun Min Cho, Su Bin Bae, Shin Il Choi, Sang Gab Kim
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Patent number: 10720501Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.Type: GrantFiled: September 9, 2019Date of Patent: July 21, 2020Assignee: Samsung Display Co., Ltd.Inventors: Yu-Gwang Jeong, Shin-Il Choi, Su-Bin Bae, Sung-Hoon Yang
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Patent number: 10672799Abstract: A display device may include a substrate, an active pattern layer, a gate insulating layer, a first metal pattern layer, an interlayer insulating layer, a second metal pattern layer, and a passivation film. The active pattern layer may be disposed on the substrate. The gate insulating layer may be disposed on the active pattern layer. The first metal pattern layer may be disposed on the gate insulating layer. The interlayer insulating layer may be disposed on the first metal pattern layer. The second metal pattern layer may be disposed on the interlayer insulating layer. The passivation film may be disposed on the side wall of the second metal pattern layer.Type: GrantFiled: March 21, 2017Date of Patent: June 2, 2020Assignee: Samsung Display Co., Ltd.Inventors: Yu Gwang Jeong, Su Bin Bae, Hyun Min Cho, Sang Gab Kim
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Publication number: 20200091393Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Su Bin BAE, Yu Gwang JEONG, Shin Il CHOI, Joon Geol LEE, Sang Gab KIM
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Publication number: 20200058727Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.Type: ApplicationFiled: July 24, 2019Publication date: February 20, 2020Inventors: Sang Gab KIM, Hyun Min CHO, Tae Sung KIM, Yu-Gwang JEONG, Su Bin BAE, Jin Seock KIM, Sang Gyun KIM, Hyo Min KO, Kil Won CHO, Han Sol LEE
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Publication number: 20200006503Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Yu-Gwang JEONG, Shin-Il CHOI, Su-Bin BAE, Sung-Hoon YANG
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Patent number: 10490537Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.Type: GrantFiled: July 5, 2018Date of Patent: November 26, 2019Assignee: Samsung Display Co., Ltd.Inventors: Su Bin Bae, Yu Gwang Jeong, Shin Il Choi, Joon Geol Lee, Sang Gab Kim
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Publication number: 20190348297Abstract: A connecting structure of a conductive layer includes a first conductive layer, a first insulating layer disposed on the first conductive layer and including a first opening overlapping the first conductive layer, a connecting conductor disposed on the first insulating layer and connected to the first conductive layer through the first opening, an insulator island disposed on the connecting conductor, a second insulating layer disposed on the first insulating layer and including a second opening overlapping the connecting conductor and the insulator island, and a second conductive layer disposed on the second insulating layer and connected to a connecting electrode through the second opening. A sum of a thickness of the first insulating layer and a thickness of the second insulating layer is greater than or equal to 1 ?m, and each of the thicknesses of the first and second insulating layers is less than 1 ?m.Type: ApplicationFiled: March 8, 2019Publication date: November 14, 2019Inventors: SU BIN BAE, YU-GWANG JEONG, SHIN IL CHOI, SANG GAB KIM, JOON GEOL LEE
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Patent number: 10438974Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.Type: GrantFiled: January 27, 2015Date of Patent: October 8, 2019Assignee: Samsung Display Co., Ltd.Inventors: Yu-Gwang Jeong, Shin-Il Choi, Su-Bin Bae, Sung-Hoon Yang
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Publication number: 20190280067Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.Type: ApplicationFiled: January 29, 2019Publication date: September 12, 2019Inventors: Yu-Gwang JEONG, Su Bin BAE, Joon Geol LEE, Sang Gab KIM, Shin Il CHOI
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Publication number: 20190172819Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.Type: ApplicationFiled: July 5, 2018Publication date: June 6, 2019Inventors: Su Bin BAE, Yu Gwang JEONG, Shin Il CHOI, Joon Geol LEE, Sang Gab KIM
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Publication number: 20190123065Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.Type: ApplicationFiled: December 10, 2018Publication date: April 25, 2019Inventors: Yu-Gwang JEONG, Hyun Min CHO, Su Bin BAE, Shin II CHOI, Sang Gab KIM