Abstract: A printed circuit board and a transmitting/receiving module including the same are disclosed. The printed circuit board in accordance with an embodiment of the present invention can include a substrate, a first transmission line, which is formed on one surface of the substrate and transmits an inputted data signal, and a second transmission line, which is capacitively connected to the first transmission line. Here, the first transmission line and the second transmission line transmit an ascending edge and a descending edge of the inputted data signal.

Abstract: A printed circuit board is disclosed. The printed circuit board in accordance with an embodiment of the present invention can include an insulation substrate, a first ground, which is formed on one surface of the insulation substrate and connected to a first power source, a second ground, which is formed on one surface of the insulation substrate and connected to a second power source, a separator, which separates the first ground from the second ground, a first signal line, which is stacked on at least one of the first ground and the second ground, and a second signal line, which is stacked on at least one of the first ground and the second ground and is adjacent to the first signal line. The separator can include a curved part, which is bent in between the first signal line and the second signal line.

Abstract: Provided are an integrated passive device (IPD) and an IPD transformer. The integrated passive device includes a dielectric laminated substrate, a first conductive layer, a buffer layer, and a second conductive layer. The first conductive layer is formed in the dielectric laminated substrate. The buffer layer is formed on one region of the first conductive layer in the dielectric laminated substrate. The second conductive layer is formed on the buffer layer such that a portion of the second conductive layer is exposed to the outside of the dielectric laminated substrate.

Abstract: A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer.

Abstract: A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through Nth latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through Nth latching units. Each of the first through Nth latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer.