Patents by Inventor Su Chen

Su Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Replacement gate structures for transistor devices
    Patent number: 9953978
    Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 24, 2018
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Kisik Choi, Su Chen Fan, Shom Ponoth
  • Gate tie-down enablement with inner spacer
    Patent number: 9941163
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 10, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Gate tie-down enablement with inner spacer
    Patent number: 9929049
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 27, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION
    Publication number: 20180083117
    Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • Replacement metal gate stack for diffusion prevention
    Patent number: 9905665
    Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • Gate tie-down enablement with inner spacer
    Patent number: 9899259
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Wimpy and nominal semiconductor device structures for vertical finFETs
    Patent number: 9881842
    Abstract: A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Su Chen Fan, Catherine B. Labelle, Xin Miao
  • GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
    Publication number: 20170372959
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • SKULLCAP WITH FULL SIZE IMAGE AND METHOD OF MAKING THE SAME
    Publication number: 20170367422
    Abstract: A method comprising steps: (a) providing an image; (b) opening the image in a photo editing software program; (c) importing a skullcap shape having four equal triangular curve portions into the photo editing software program; (d) editing the image to match the skullcap shape and triangular curve portions; (e) printing the edited image to a medium; (f) separating the four triangular curve portions of the printed image; and (g) sewing the four separate triangular curve portions into a skullcap.
    Type: Application
    Filed: December 27, 2016
    Publication date: December 28, 2017
    Applicant: Pic-A-Kippa LLC
    Inventors: URI TURK, SU CHEN
  • Securing database content
    Patent number: 9798771
    Abstract: Content is secured in a database. One or more columns in challenge tables are identified, and values from the challenge tables are retrieved. A database query may execute in response to a match between the values from the challenge tables and query data. However, if the query data fails to match the values from the challenge tables, execution of the database query may be disallowed.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 24, 2017
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Divesh Srivastava, Lakshmanan Sundaram Viravanallur, Su Chen, Xin Dong
  • Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer
    Patent number: 9786607
    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sukwon Hong, William J. Taylor, Jr.
  • GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
    Publication number: 20170278753
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Gate tie-down enablement with inner spacer
    Patent number: 9735054
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 15, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
    Patent number: 9728456
    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sukwon Hong, William J. Taylor, Jr.
  • Stable multiple threshold voltage devices on replacement metal gate CMOS devices
    Patent number: 9728462
    Abstract: A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is formed on the fin, and an interlayer dielectric layer is formed on the epitaxial layer. Spacers on the fin define the narrow channel and the long channel. A high-k dielectric material is deposited in the narrow and long channels. A metal layer is deposited on the high-k dielectric material in the narrow and long channels. A height of the high-k dielectric material in the narrow channel is recessed. The metal layer is removed from the narrow and long channels. A work function metal is deposited in the narrow and long channels. A gate conduction metal is deposited to fill the narrow channel and long channel. A capping layer is deposited on the top surface of the structure.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
  • MESSAGE PUSHING METHOD AND MESSAGE PUSHING DEVICE
    Publication number: 20170180501
    Abstract: A message pushing method and a message pushing device are provided. The message pushing method includes the following steps. Acquire a portrait image from a scene image, and obtain an attribute, representing the portrait image, by extracting features of a body part shown in the portrait image. Select one of a plurality of pushing information according to the attribute of the portrait image. The selected pushing information has a second image. Obtain a first image by performing an image processing procedure to the portrait image, and produce a synthesis image by combining the first image and the second image. Display the synthesis image to an attracted-viewer relating to the portrait image.
    Type: Application
    Filed: November 10, 2016
    Publication date: June 22, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jian-Ren CHEN, Su-Chen HUANG, Chun-Yen CHEN, Szu-Hsien YEH, Chao-Wang HSIUNG
  • Namespace mirroring in an expandable storage volume
    Patent number: 9684571
    Abstract: Technology for maintaining a backup of namespace metadata of an expandable storage volume is disclosed. In various embodiments, the expandable storage volume backs up metadata of a namespace constituent volume of the expandable storage volume into a namespace mirror volume. The namespace constituent volume is responsible for storing the metadata for data objects stored in multiple data constituent volumes of the expandable storage volume. In response to a signal indicating that the namespace constituent volume is unavailable, the namespace mirror volume replaces the role of the namespace constituent volume. The new namespace constituent volume continues to provide metadata for a data object of the data objects in response to an operation request for the data object.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: June 20, 2017
    Assignee: NETAPP, INC.
    Inventors: Kiran Kumar Modukuri, Su Chen
  • LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
    Publication number: 20170170118
    Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.
    Type: Application
    Filed: August 30, 2016
    Publication date: June 15, 2017
    Inventors: Su Chen Fan, Vimal Kamineni, Andre P. Labonte, Ruilong Xie
  • GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
    Publication number: 20170170070
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
    Publication number: 20170162438
    Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 8, 2017
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta