Patents by Inventor Su-Chia Lu

Su-Chia Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls
    Patent number: 7348271
    Abstract: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 25, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Yuan-Chang Huang, Shyh-Ming Chang, Su-Chia Lu
  • Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls
    Publication number: 20070111382
    Abstract: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
    Type: Application
    Filed: December 22, 2006
    Publication date: May 17, 2007
    Inventors: Yuan-Chang Huang, Shyh-Ming Chang, Su-Chia Lu
  • Conductive bumps with non-conductive juxtaposed sidewalls
    Patent number: 7154176
    Abstract: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: December 26, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Yuan-Chang Huang, Shyh-Ming Chang, Su-Chia Lu
  • Conductive bumps with non-conductive juxtaposed sidewalls and method for fabricating
    Publication number: 20050104223
    Abstract: A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Yuan-Chang Huang, Shyh-Ming Chang, Su-Chia Lu