Patents by Inventor Su-Chun YANG

Su-Chun YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163835
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 10034390
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 9978709
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn—Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Publication number: 20180108632
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 19, 2018
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Chih-Hang TUNG, Chen-Hua YU
  • Patent number: 9893046
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20180012880
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU
  • Patent number: 9842817
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20170330855
    Abstract: A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Chih-Hang Tung, Su-Chun Yang, Tung-Liang Shao, Chen-Hua Yu
  • Publication number: 20170012019
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Su-Chun YANG, Chung-Jung WU, Hsiao-Yun CHEN, Yi-Li HSIAO, Chih-Hang TUNG, Da-Yuan SHIH, Chen-Hua YU
  • Patent number: 9475145
    Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Publication number: 20160143157
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 9263407
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Publication number: 20150079763
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 19, 2015
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20140262470
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Application
    Filed: June 25, 2013
    Publication date: September 18, 2014
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Publication number: 20130221074
    Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chang WEI, Su-Chun YANG, Hsiao-Yun CHEN, Chih-Hang TUNG, Da-Yuan SHIH, Chen-Hua YU