Patents by Inventor Su-Fei LIN

Su-Fei LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230154880
    Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 18, 2023
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
  • Patent number: 11594508
    Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
  • Publication number: 20220351983
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
  • Patent number: 11417539
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Su-Fei Lin, Hsu-Lun Liu, Chien-Pin Chan, Yung-Sheng Lin
  • Publication number: 20210375815
    Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.
    Type: Application
    Filed: October 13, 2020
    Publication date: December 2, 2021
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin
  • Publication number: 20210272819
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Application
    Filed: October 30, 2020
    Publication date: September 2, 2021
    Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN