Patents by Inventor Su Fu

Su Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220392460
    Abstract: Disclosed are systems and methods to modify the Bluetooth mono HFP protocol to support bi-directional stereo operation for high bandwidth audio including 12-KHz wide-band, 16-KHz super wide-band (SWB), and 24-KHz full band (FB) audio. The techniques leverage the larger packet size and longer duty cycle of the 2-EV5 transport packet and expand the block size of the audio frames generated by the AAC-ELD codec to increase the maximum data throughput from the 64 kbps of the mono HFP protocol to 192 kbps using a stereo HFP protocol. The increased throughput not only supports stereo operations, but allows the transport of redundant or FEC packets for increased robustness against packet loss. In one aspect, the AAC-ELD codec may be configured for dynamic bit rate switching to flexibly perform trade-offs between audio quality and robustness against packet loss. The stereo HFP may configure the maximum throughput based on the desired audio quality.
    Type: Application
    Filed: May 11, 2022
    Publication date: December 8, 2022
    Inventors: Aarti Kumar, Eric A. Allamanche, Su Fu, Leijun Dong
  • Patent number: 9012332
    Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Inventors: Hui-Ping Chiang, Su-Fu Lee, Hsiu-Ying Hsu
  • Publication number: 20130240255
    Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 19, 2013
    Inventors: Hui-Ping Chiang, Su-Fu Lee, Hsiu-Ying Hsu