Patents by Inventor Su-gon Bae

Su-gon Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7709340
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Patent number: 7534677
    Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyae-ryoung Lee, Su-gon Bae
  • Publication number: 20090051014
    Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.
    Type: Application
    Filed: October 15, 2008
    Publication date: February 26, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
  • Publication number: 20070187770
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 16, 2007
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Publication number: 20060163669
    Abstract: A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 27, 2006
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Su-gon Bae
  • Publication number: 20050170575
    Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.
    Type: Application
    Filed: January 14, 2005
    Publication date: August 4, 2005
    Inventors: Hyae-ryoung Lee, Su-gon Bae