Abstract: A processing tool includes a chamber configured to receive a wafer, the chamber having a sidewall and a sidewall heating source configured to heat the sidewall of the chamber. The processing tool further includes a first heating source configured to provide energy to an interior of the chamber through a top surface of the chamber and a second heating source configured to provide energy to the interior of the chamber through a bottom surface of the chamber. The sidewall heating source is separate from the first heating source and the second heating source.

Abstract: The disclosure provides a real-time wafer breakage detection method. The detection method includes the following operations. A wafer is positioned on a wafer holder of a process chamber in which a thermal process is being performed. Then, the temperature at the wafer holder is measured. And, a notification for corrective action is issued if the temperature is out of a predetermined alarm range.

Abstract: A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region.

Abstract: The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions.

Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.

Abstract: A processing tool includes a chamber configured to receive a wafer, the chamber having a sidewall and a sidewall heating source configured to heat the sidewall of the chamber. The processing tool further includes a first heating source configured to provide energy to an interior of the chamber through a top surface of the chamber and a second heating source configured to provide energy to the interior of the chamber through a bottom surface of the chamber. The sidewall heating source is separate from the first heating source and the second heating source.

Abstract: The disclosure provides a real-time wafer breakage detection method. The detection method includes the following operations. A wafer is positioned on a wafer holder of a process chamber in which a thermal process is being performed. Then, the temperature at the wafer holder is measured. And, a notification for corrective action is issued if the temperature is out of a predetermined alarm range.

Abstract: The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

Abstract: A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a multi-composition ILD layer by forming a first portion of an inter-layer dielectric (ILD) layer on a semiconductor substrate; and forming a second portion of an ILD layer on the first portion of the ILD layer. The second portion may have a greater silicon content than the first portion. For example, the second portion may be a silicon rich oxide.

Abstract: An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.

Abstract: The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions.

Abstract: A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region.

Abstract: The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

Abstract: The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

Abstract: The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

Abstract: An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.