Patents by Inventor Su-Hwa Tsai

Su-Hwa Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806150
    Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: October 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Su-Hwa Tsai
  • Publication number: 20170236899
    Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Inventors: Shih-Yin Hsiao, Su-Hwa Tsai
  • Patent number: 9680010
    Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Su-Hwa Tsai
  • Patent number: 9136375
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Te Lee, Ming-Shun Hsu, Ke-Feng Lin, Chih-Chung Wang, Hsuan-Po Liao, Shih-Teng Huang, Shu-Wen Lin, Su-Hwa Tsai, Shih-Yin Hsiao
  • Publication number: 20150137228
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Te Lee, Ming-Shun Hsu, Ke-Feng Lin, Chih-Chung Wang, Hsuan-Po Liao, Shih-Teng Huang, Shu-Wen Lin, Su-Hwa Tsai, Shih-Yin Hsiao