Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

Abstract: Provided are a psoriasis-induced transgenic animal model overexpressing the Pellino homolog 1 (Peli1) gene according to doxycycline administration, and a use thereof. The transgenic animal model of the present disclosure exhibited similarity to phenotypes shown in patients with psoriasis, due to overexpression of the Pellino homolog 1 (Peli1) gene according to doxycycline administration. It is anticipated that the transgenic animal model may be usefully used in clinical studies, such as screening for a candidate drug for the treatment of psoriasis. Additionally, it is anticipated that a peptide derived from the Peli1 FHA domain targeting the FHA binding motif that inhibits normal substrate binding between a substrate protein and the Peli1 protein may be usefully used in the development of new drugs for psoriasis-associated diseases. Moreover, by confirming an expression level of the Peli1 protein, it is anticipated to be usefully used in evaluating the severity of patients with psoriasis.

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: Disclosed is a lamp switch for a parking brake and a structure of a lamp switch is configured to be changed, which indicates that a parking brake is pulled as lighting a lamp on a instrument panel of a vehicle by pulling a lever for the parking brake to prevent malfunction due to poor contact of the lamp switch when an external shock occurs, enhance fuel efficiency and reduce manufacturing cost due to weight reduction, and reduce the number of assembled fixtures.

Abstract: A terminal fixed lamp switch for a parking brake and a structure of a lamp switch is configured to be changed, which indicates that a parking brake is pulled as lighting a lamp on an instrument panel of a vehicle by pulling a lever for the parking brake to prevent malfunction due to poor contact of the lamp switch when an external shock occurs, and enhance fuel efficiency and reduce manufacturing cost due to weight reduction.

Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided.

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Abstract: Disclosed is an organic light-emitting display device, which prevents lateral current leakage by providing a structure on a bank so as to cut off an organic material, which is formed in a subsequent process, around the structure.

Abstract: Disclosed is a lamp switch for a parking brake and a structure of a lamp switch is configured to be changed, which indicates that a parking brake is pulled as lighting a lamp on a instrument panel of a vehicle by pulling a lever for the parking brake to prevent malfunction due to poor contact of the lamp switch when an external shock occurs, enhance fuel efficiency and reduce manufacturing cost due to weight reduction, and reduce the number of assembled fixtures.

Abstract: A lubrication system of a transmission provides oil passages in an upper portion of a transmission case, and an oil dispensing guider at the transmission case for dispensing churning oil to the oil passages. The oil dispensing guider includes a guiding surface bent at multiple points along a length direction so as to fit bottoms of the oil passages, a slanted guide surface formed along the guiding surface and being slant upward so as to guide oil on the slanted guide surface to the guiding surface, sockets integrally formed at the guiding surface and respectively inserted into the oil passages, and an oil collecting portion formed along an exterior edge of the guiding surface and the slanted guide surface and bent from the exterior edge so as to collect the churning oil splashed toward the oil dispensing guider.

Abstract: A lubrication system of a transmission includes a plurality of oil passages formed in an upper portion of a transmission case and supplied with churning oil, a plurality of oil outlets branched from respective oil passages formed in the transmission case and allowing oil supplied from the oil passages to free-fall, and an oil collecting portion formed at an interior of the case wall between the gear case and the motor case. In particular, the oil collecting portion collects oil free-falling from at least one oil outlet branched from at least one oil passage at the gear case, through a through-hole formed at a case wall of the gear case, and then supplies the collected oil to an exterior lubrication portion.

Abstract: Disclosed is a terminal fixed lamp switch for a parking brake and a structure of a lamp switch is configured to be changed, which indicates that a parking brake is pulled as lighting a lamp on a instrument panel of a vehicle by pulling a lever for the parking brake to prevent malfunction due to poor contact of the lamp switch when an external shock occurs, and enhance fuel efficiency and reduce manufacturing cost due to weight reduction.

Abstract: An organic light-emitting device is configured such that, in a plurality of stacks in which the optical distance is adjusted using the thickness of an emission layer, the structure of the emission layer is changed to reduce the drive voltage and increase the lifespan thereof, and an organic light-emitting display device using the same.

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Abstract: Disclosed herein is a display panel including a polarizing emission layer. An organic light emitting device is formed on a first substrate. A polarizing emission layer are formed on a second substrate facing the first substrate. The polarizing emission layer is formed in a subpixel area corresponding to the organic light emitting device. The polarizing emission layer includes quantum rods. The quantum rods are aligned in one direction to be polarized. Accordingly, loss of transmitting light in the display panel including the polarizing layer may be minimized. In addition, since colors are implemented by the quantum rods included in the polarizing emission layer, color filters can be replaced by the quantum rods, and loss of light resulting from the color filters may be minimized.

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided.