Abstract: Provided is a refrigerator including a main body, a storage compartment provided inside the main body with a front side that is open, a drawer-type door slidably coupled to the main body to open and close the storage compartment, and including a door cap having a handle pocket, and a door opening device coupled to the door cap and configured to open the drawer-type door. The door opening device includes a handle lever rotatably coupled to the door cap. The door opening device includes a slider disposed at a rear of the handle lever to perform straight linear motion in an upper-to-lower direction by the handle lever. The door opening device includes a pusher coupled at a rear of the slider to perform straight linear motion in a front-to-rear direction, and, while the slider is moving upward, perform straight linear motion rearward to press the main body to open the drawer-type door.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.

Abstract: Provided is a method of manufacturing a semiconductor device, the method including: forming a mold structure comprising insulation layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a channel hole extending through the mold structure; forming a blocking layer in the channel hole; forming a charge storage layer on the blocking layer; forming a tunnel insulation layer including a doping element on the charge storage layer; performing heat treatment to diffuse the doping element from the tunnel insulation layer to the charge storage layer; and forming a channel layer on the tunnel insulation layer.

Abstract: A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm?3 to about 10×1019 cm?3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

Abstract: A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: The present invention relates to a case assembly for a mobile terminal. The case assembly according to an aspect includes a rear surface case detachably coupled to a rear surface of a terminal body to cover the rear surface of the terminal body, a rear cover coupled to a rear surface of the rear surface case to protect the rear surface of the rear surface case, and an adhesive sheet provided between the rear surface case and the rear cover to provide an adhesive force to opposite surfaces so as to couple the rear cover to the rear surface of the rear surface case, wherein adhesive parts configured to couple the rear cover and the rear surface case to each other along an edge of the rear surface case are formed in the edge of the rear surface case and an area of the rear cover, which covers the edge of the rear surface case.

Abstract: The present invention relates to a case assembly for a mobile terminal. The case assembly according to an aspect includes a rear surface case detachably coupled to a rear surface of a terminal body to cover the rear surface of the terminal body, a rear cover coupled to a rear surface of the rear surface case to protect the rear surface of the rear surface case, and an adhesive sheet provided between the rear surface case and the rear cover to provide an adhesive force to opposite surfaces so as to couple the rear cover to the rear surface of the rear surface case, wherein adhesive parts configured to couple the rear cover and the rear surface case to each other along an edge of the rear surface case are formed in the edge of the rear surface case and an area of the rear cover, which covers the edge of the rear surface case.

Abstract: There is disclosed a mobile terminal including a front case, a first rear case shaped to cover a first area of a rear surface of the front case, a second rear case shaped to cover the second area of the rear surface of the front case, a tightening groove formed in the portion where the first rear case and the second rear case are coupled with each other and comprising inclined surfaces a first tightening rib projected from a front surface of the first rear case and comprising an inclined surface corresponding to one inclined surface of the tightening groove, a second tightening rib projected from the front surface of the second rear case and comprising an inclined surface corresponding to the other inclined surface of the tightening groove, wherein the first tightening rib and the second tightening rib are inserted in the tightening groove.

Abstract: There is disclosed a mobile terminal including a front case, a first rear case shaped to cover a first area of a rear surface of the front case, a second rear case shaped to cover the second area of the rear surface of the front case, a tightening groove formed in the portion where the first rear case and the second rear case are coupled with each other and comprising inclined surfaces a first tightening rib projected from a front surface of the first rear case and comprising an inclined surface corresponding to one inclined surface of the tightening groove, a second tightening rib projected from the front surface of the second rear case and comprising an inclined surface corresponding to the other inclined surface of the tightening groove, wherein the first tightening rib and the second tightening rib are inserted in the tightening groove.