Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.

Abstract: A display apparatus includes: a display panel including a gate line, a storage line adjacent to the gate line, and a pixel, the pixel including a pixel transistor coupled to the gate line, a liquid crystal (“LC”) capacitor coupled to the pixel transistor, and a storage capacitor coupled to the LC capacitor; a first gate driver configured to provide a gate signal to the gate line; and a first level switch configured to provide a storage signal to the storage line, the storage signal being synchronized with the gate signal and having a phase opposite to a phase of the gate signal.

Abstract: A data driver includes shift registers, sampling latches, holding latches, and a data sensing unit. The shift registers generate sampling pulses by shifting a source start pulse in response to a source sampling clock. Each of the sampling latches receives current data and stores the current data in response to each of the sampling pulses. Each of the holding latches receives the current data stored in each of the sampling latches, and stores the received current data in response to a source output enable signal. The data sensing unit receives the current data corresponding to an i-th sampling latch of the sampling latches or an i-th holding latch of the holding latches (i is a positive integer) and previous data stored in the i-th sampling latch or the i-th holding latch, compares the current data with the previous data, and generates control data based on the comparison result.

Abstract: A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.

Abstract: A gate driver includes stages configured to output gate signals and gate initialization signals. Here, an Nth stage includes a first output block configured to generate an Nth carry signal based on an N?1th carry signal and to generate an Nth gate initialization signal based on the N?1th carry signal, an output enable signal, and an output disable signal that is an inverted signal of the output enable signal; and a second output block configured to generate an Nth gate signal by shifting the Nth gate initialization signal by a horizontal time, where N is a positive integer.

Abstract: A display device includes a display panel, a controller, a power supplier, and an initialization voltage generator. The controller generates a power control signal based on an input image. The power supplier generates a variable driving voltage that is changed based on the power control signal. The initialization voltage generator changes an initialization voltage to initialize the pixels based on the variable driving voltage.

Abstract: There is provided a scan driver including a plurality of stages coupled to respective scan lines, wherein a kth (where k is a natural number) stage of the plurality of stages includes: a first driver configured to supply a kth scan signal to a first output terminal, based on a first clock signal, and a second driver configured to supply a kth carry signal not overlapping the kth scan signal to a second output terminal, based on an inverse first clock signal.

Abstract: A display apparatus includes an image analyzer that analyzes image data and outputs an interrupt signal at a period during which the image data of a low frequency change to the image data of a high frequency, a frequency detector that detects the high frequency, a frame rate controller that outputs a vertical synch signal of the high frequency in response to the interrupt signal, a polarity compensation controller that determines a last frame of the low frequency based on an interrupt period at which the interrupt signal is generated, generates a reversed polarity signal with respect to a polarity signal of the last frame and outputs the reversed polarity signal during a polarity compensation period close to the interrupt period, and a data driver circuit that outputs a data signal based on the reversed polarity signal to a data line during the polarity compensation period.

Abstract: There is provided a pixel including an organic light emitting diode (OLED), a first transistor having a first electrode connected to a first power source and configured to control an amount of current supplied from the first power source to the OLED in response to a data signal, a second transistor and a third transistor connected between a second electrode and a gate electrode of the first transistor, and a fourth transistor connected between an initializing power source and a first node that is a common node of the second transistor and the third transistor.

Abstract: A method of driving a display panel includes generating a first driving period having a first driving frequency, generating a second driving period having a second driving frequency, and inserting a compensating frame between the first driving period and the second driving period. A display apparatus includes a display panel configured to display an image, and a display panel driver configured to generate a first driving period having a first driving frequency, to generate a second driving period having a second driving frequency, and to insert a compensating frame between the first driving period and the second driving period.

Abstract: A liquid crystal display includes a liquid crystal panel which includes a plurality of pixels and a plurality of data lines connected to the plurality of pixels and a data driver which applies data voltages having different polarities to adjacent data lines among the plurality of data lines and performs a first charge sharing to short the data lines having the different polarities and a second charge sharing to short the data lines having the same polarity, wherein the voltage of at least one of the data lines is step-wisely changed by the second charge sharing.

Abstract: A data driver including a power control part configured to control power according to mode signal determined based on an input image, a digital to analog converting part configured to convert a digital data signal into an analog data voltage, a buffering part configured to buffer the data voltage, a first switching part configured to apply the data voltage to a data line in a normal mode, when turned on, and a second switching part configured to apply a blank voltage to the data line in a blank period of a low frequency mode, when turned on.

Abstract: A scan driver of an organic light emitting diode (OLED) display device includes a plurality of sequentially-connected stages each connected to a plurality of pixels through a plurality of first-scan lines and a plurality of second-scan lines. Each stage of the sequentially-connected stages includes a common driver and a sub-driver unit. The common driver is configured to concurrently provide a common first-scan signal to the first-scan lines of the stage in response to at least a first initialization signal and a second initialization signal. The sub-driver unit is configured to serially provide second-scan signals to the second-scan lines of the stage in response to a plurality of output enable signals, the first-scan signal, and one of the first initialization signal and the second initialization signal. An order of the serial providing of the second-scan signals to the second-scan lines is dynamically configurable based on the output enable signals.

Abstract: A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.

Abstract: A method of driving a display panel includes dividing an input image into a plurality of segments; generating flicker levels of respective ones of the segments; determining a frame rate of the display panel based on the flicker levels of the segments; and outputting a data voltage to the display panel at the frame rate.

Abstract: A liquid crystal display includes: a display panel; a signal controller configured to receive an input image signal and an input control signal, output an output image signal and an output control signal, and determine a charge sharing between two or more data lines having voltages in the same polarity; and a data driver configured to convert, based on the output control signal, the image signal into data voltages to be supplied to the data lines connected to the pixels, the data voltages having positive levels and negative levels. The data driver is further configured to perform a first charge sharing by short-circuiting first and second data lines that are adjacent to each other, and a second charge sharing by short-circuiting third and fourth data lines having data voltages in the same polarity, wherein the first charge sharing and the second charge sharing may not temporally overlap with each other.