Abstract: A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.

Abstract: A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.

Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation.