Patents by Inventor Su-Jen Sung
Su-Jen Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10867920Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.Type: GrantFiled: December 20, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Publication number: 20200111744Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Inventor: Su-Jen Sung
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Patent number: 10510666Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.Type: GrantFiled: February 22, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Su-Jen Sung
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Publication number: 20190148308Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Publication number: 20190148307Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first capping layer on a dielectric structure over a substrate, and patterning the dielectric structure and the first capping layer to define cavities within the dielectric structure. A conductive material is formed within the cavities and a second capping layer is formed on the conductive material. An etch stop layer is formed along sidewalls and over an upper surface of the second capping layer. The etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer. The first thickness is greater than the second thickness.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Chao-Chun Wang, Su-Jen Sung
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Patent number: 10163794Abstract: The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.Type: GrantFiled: May 11, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Chun Wang, Su-Jen Sung
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Patent number: 10163795Abstract: The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.Type: GrantFiled: November 4, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Patent number: 9852905Abstract: The present disclosure is directed an apparatus for regulating gas flow in a deposition chamber during a deposition process. The apparatus includes an interior wall that forms an accommodating portion that accommodates a wafer support structure and an exterior wall disposed opposite the interior wall. The apparatus further includes an upper surface, coupled to both the interior wall and the exterior wall, that has a plurality of openings therethrough. The plurality of openings are configured to distribute a flow of gas originating above the apparatus when the apparatus is positioned over a gas outlet port of the deposition chamber.Type: GrantFiled: January 16, 2014Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Su-Jen Sung
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Publication number: 20170162506Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventor: Su-Jen Sung
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Publication number: 20170053875Abstract: The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer.Type: ApplicationFiled: November 4, 2016Publication date: February 23, 2017Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Patent number: 9530728Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: GrantFiled: September 4, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Patent number: 9490209Abstract: Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.Type: GrantFiled: August 15, 2013Date of Patent: November 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Publication number: 20160254226Abstract: The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Chao-Chun Wang, Su-Jen Sung
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Patent number: 9396990Abstract: The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.Type: GrantFiled: January 31, 2013Date of Patent: July 19, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Chun Wang, Su-Jen Sung
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Patent number: 9355894Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: May 6, 2015Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150380352Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventors: Su-Jen Sung, Yi-Nien Su
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Patent number: 9129965Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: GrantFiled: May 8, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150235894Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: ApplicationFiled: May 6, 2015Publication date: August 20, 2015Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150197846Abstract: The present disclosure is directed an apparatus for regulating gas flow in a deposition chamber during a deposition process. The apparatus includes an interior wall that forms an accommodating portion that accommodates a wafer support structure and an exterior wall disposed opposite the interior wall. The apparatus further includes an upper surface, coupled to both the interior wall and the exterior wall, that has a plurality of openings therethrough. The plurality of openings are configured to distribute a flow of gas originating above the apparatus when the apparatus is positioned over a gas outlet port of the deposition chamber.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Su-Jen SUNG
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Patent number: 9041216Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: June 19, 2013Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su