Patents by Inventor Su-Jeong PARK
Su-Jeong PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111194Abstract: A display device includes a substrate, conductive pads arranged on the substrate over a plurality of rows, and a drive circuit chip including bumps arranged over a plurality of rows to be electrically connected with the conductive pads, and the conductive pads arranged in a same row are arranged in parallel, and the bumps arranged in a same row are arranged in a zigzag form so as to be partially shifted.Type: ApplicationFiled: December 12, 2023Publication date: April 4, 2024Inventors: Han Ho PARK, Dae Geun LEE, Su Jeong KIM, Sang Won YEO, Kyung Mok LEE, Wu Hyen JUNG
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Patent number: 11943490Abstract: The method comprises registering at least one of an internet protocol (IP) address and a media access control (MAC) address of the security devices, generating a plurality of public key and private key pairs, encrypting and storing private keys comprised in the plurality of public key and private key pairs using a master key provided from a master key management unit, selecting any one of a plurality of public key and private key pairs when the access of the security device is approved and providing a certificate comprising the selected public key to the security device, receiving a symmetric key encrypted with the public key of the certificate from the security device, and decrypting the private key using the master key provided from the master key management unit.Type: GrantFiled: January 11, 2022Date of Patent: March 26, 2024Assignee: DUDU Information Technologies, Inc.Inventors: Young Sun Park, Su Man Nam, Jin Woo Lee, Jun Geol Kim, Yun Seong Kim, Yoon Jeong Kim
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Publication number: 20230282528Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.Type: ApplicationFiled: August 29, 2022Publication date: September 7, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Bin SEO, Su Jeong PARK, Seok Ho KIM, Kwang Jin MOON
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Patent number: 11600552Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: June 10, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Patent number: 11488860Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: GrantFiled: July 24, 2020Date of Patent: November 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-Il Choi, Atsushi Fujisaki
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Publication number: 20210296211Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: ApplicationFiled: June 10, 2021Publication date: September 23, 2021Inventors: Ju-Bin SEO, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Patent number: 11043445Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: GrantFiled: April 17, 2019Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin Seo, Su-Jeong Park, Tae-Seong Kim, Kwang-Jin Moon, Dong-Chan Lim, Ju-Il Choi
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Publication number: 20200357690Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju Bin SEO, Ju-Il CHOI, Atsushi FUJISAKI
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Patent number: 10763163Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: GrantFiled: January 8, 2019Date of Patent: September 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-il Choi, Atsushi Fujisaki
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Publication number: 20200144158Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.Type: ApplicationFiled: April 17, 2019Publication date: May 7, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Bin SEO, Su-Jeong PARK, Tae-Seong KIM, Kwang-Jin MOON, Dong-Chan LIM, Ju-Il CHOI
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Publication number: 20200075524Abstract: A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided.Type: ApplicationFiled: March 18, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Bin SEO, Dong Hoon LEE, Ju Il CHOI, Su Jeong PARK, Dong Chan LIM
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Publication number: 20200027784Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: ApplicationFiled: January 8, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju-bin SEO, Ju-ll CHOI, Atsushi FUJISAKI
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Publication number: 20170205382Abstract: The present invention relates to a real-time automatic analysis method, for an organic contaminant, using a real-time SPME-GC or SPME-GC/MS analysis system, the method comprising: a sample supply step for supplying consecutively and in real time a sample to a storing portion of a sample bottle through a sample supply line formed in a real-time SPME-GC or SPME-GC/MS analysis system; and a sample analysis step, such that the sample can be supplied consecutively and in real time, and thus a point of generation of a high-concentration organic contaminant is accurately and quickly identified and follow-up measures are taken.Type: ApplicationFiled: September 23, 2015Publication date: July 20, 2017Inventors: In-Cheol CHOI, Hyen-Mi CHUNG, Weo-Hwa JHEONG, Oh-Sang KWON, Dong-Hwan JEONG, Su-Jeong PARK, Yang-Seok CHO