Patents by Inventor Su-Jin Chae
Su-Jin Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140242773Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: SK hynix Inc.Inventors: Su Jin CHAE, Jin Hyock KIM, Young Seok KWON
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Patent number: 8748860Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.Type: GrantFiled: December 12, 2012Date of Patent: June 10, 2014Assignee: SK Hynix Inc.Inventors: Su Jin Chae, Jin Hyock Kim, Young Seok Kwon
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Publication number: 20140054752Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.Type: ApplicationFiled: December 12, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventors: Su Jin CHAE, Jin Hyock KIM, Young Seok KWON
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Publication number: 20130334670Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.Type: ApplicationFiled: December 14, 2012Publication date: December 19, 2013Applicant: SK HYNIX INC.Inventors: Seung Beom BAEK, Su Jin CHAE, Min Yong LEE, Hye Jin SEO, Young Ho LEE, Jin Ku LEE, Jong Chul LEE
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Patent number: 8609503Abstract: The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.Type: GrantFiled: January 25, 2012Date of Patent: December 17, 2013Assignee: Hynix Semiconductor Inc.Inventors: Keum Bum Lee, Su Jin Chae, Hye Jin Seo
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Publication number: 20130099188Abstract: A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.Type: ApplicationFiled: December 20, 2011Publication date: April 25, 2013Inventors: Jin Hyock Kim, Su Jin Chae, Young Seok Kwon
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Publication number: 20120156851Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.Type: ApplicationFiled: January 25, 2012Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Keum Bum LEE, Su Jin CHAE, Hye Jin SEO
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Patent number: 8049199Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.Type: GrantFiled: July 8, 2008Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Yong Seok Eun, Su Jin Chae, Keum-Bum Lee, Heon-Yong Chang, Min-Yong Lee
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Publication number: 20110073826Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.Type: ApplicationFiled: December 29, 2009Publication date: March 31, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Keum Bum LEE, Su Jin CHAE, Hye Jin SEO
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Patent number: 7772101Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.Type: GrantFiled: June 25, 2008Date of Patent: August 10, 2010Assignee: Hynix Semiconductor Inc.Inventors: Su-Jin Chae, Keum-Bum Lee, Min-Yong Lee
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Patent number: 7688570Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: GrantFiled: October 24, 2008Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Publication number: 20090321705Abstract: A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.Type: ApplicationFiled: October 22, 2008Publication date: December 31, 2009Applicant: Hynix Semiconductor, Inc.Inventors: Min Yong Lee, Su Jin Chae, Keum Bum Lee, Dong Ryeol Lee, Hyung Suk Lee
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Publication number: 20090140385Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: October 24, 2008Publication date: June 4, 2009Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Publication number: 20090045389Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.Type: ApplicationFiled: July 8, 2008Publication date: February 19, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Yong Seok Eun, Su Jin Chae, Keum Bum Lee, Heon Yong Chang, Min Yong Lee
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Publication number: 20090039334Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.Type: ApplicationFiled: June 25, 2008Publication date: February 12, 2009Applicant: Hynix Semiconductor, Inc.Inventors: Su Jin CHAE, Keum Bum LEE, Min Yong LEE
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Patent number: 7463476Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: GrantFiled: June 7, 2005Date of Patent: December 9, 2008Assignee: Hynix Semiconductor Inc.Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Publication number: 20080070398Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection.Type: ApplicationFiled: June 5, 2007Publication date: March 20, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Dong Su Park, Ho Jin Cho, Keum Bum Lee, Su Jin Chae, Cheol-Hwan Park
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Patent number: 7300852Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.Type: GrantFiled: March 24, 2005Date of Patent: November 27, 2007Assignee: Hynix Semiconductor Inc.Inventors: Ho Jin Cho, Jun Soo Chang, Eun A. Lee, Su Jin Chae, Young Dae Kim
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Publication number: 20060221548Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: June 7, 2005Publication date: October 5, 2006Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Patent number: 6869874Abstract: The present invention provides a method for forming a contact plug of a semiconductor device with a low contact resistance. The inventive method includes the steps of: forming a contact hole in an inter-layer insulating layer formed on a silicon substrate; removing a native oxide layer formed in the contact hole; forming a single crystal silicon layer on a surface of the silicon substrate in the contact hole, wherein the single crystal silicon layer is formed by an epitaxial growth performed at a first reaction chamber of which pressure is maintained less than approximately 10?6 Torr; and filling the contact hole with polysilicon, wherein the polysilicon layer is formed at a second reaction chamber.Type: GrantFiled: December 30, 2002Date of Patent: March 22, 2005Assignee: Hynix Semiconductor Inc.Inventors: Hai-Won Kim, Su-Jin Chae