Patents by Inventor Su-Jin Shin
Su-Jin Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085282Abstract: There is provide a method for manufacturing analytical semiconductor samples by using an apparatus for manufacturing analytical semiconductor samples, which minimizes a feedback time by manufacturing a viewing surface that is environment-friendly and has a large area. The method comprising mounting the analytical semiconductor samples to a holder; discharging deionized (DI) water to an upper surface of a polishing plate through a DI water nozzle; grinding the analytical semiconductor samples with the upper surface of the polishing plat; determining whether a desired viewing surface of the analytical semiconductor samples has been acquired after the grinding of the analytical semiconductor samples; and transferring the analytical semiconductor samples to analyze the viewing surface of the ground analytical semiconductor samples based on a determination that the desired viewing surface of the analytical semiconductor samples has been acquired.Type: ApplicationFiled: August 23, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Min Chul JO, Sang Hyun PARK, Su Jin SHIN, Gil Ho GU, Dae Gon YU, So Yeon LEE, Yun Bin JEONG
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Patent number: 10468431Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.Type: GrantFiled: July 5, 2018Date of Patent: November 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Ho Kim, BiO Kim, Hyung Joon Kim, Young Seon Son, Su Jin Shin, Jae Young Ahn, Ju Mi Yun, HanMei Choi
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Publication number: 20180331119Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.Type: ApplicationFiled: July 5, 2018Publication date: November 15, 2018Inventors: Jung Ho KIM, BiO KIM, Hyung Joon KIM, Young Seon SON, Su Jin SHIN, Jae Young AHN, Ju Mi YUN, HanMei CHOI
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Patent number: 10020318Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.Type: GrantFiled: July 25, 2016Date of Patent: July 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Ho Kim, BiO Kim, Hyung Joon Kim, Young Seon Son, Su Jin Shin, Jae Young Ahn, Ju Mi Yun, HanMei Choi
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Patent number: 9882085Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.Type: GrantFiled: February 10, 2016Date of Patent: January 30, 2018Assignee: Seoul Viosys Co., Ltd.Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Su Jin Shin, Ki Bum Nam, Yu Dae Han, A Ram Cha Lee
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Patent number: 9853044Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: GrantFiled: January 14, 2016Date of Patent: December 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Patent number: 9799657Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.Type: GrantFiled: June 23, 2014Date of Patent: October 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jintae Noh, Bio Kim, Su-Jin Shin, Hanvit Yang, Kihyun Hwang
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Publication number: 20170162578Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.Type: ApplicationFiled: June 23, 2014Publication date: June 8, 2017Inventors: Jintae NOH, Bio KIM, Su-Jin SHIN, Hanvit YANG, Kihyun HWANG
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Publication number: 20170077136Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.Type: ApplicationFiled: July 25, 2016Publication date: March 16, 2017Inventors: Jung Ho KIM, BiO KIM, Hyung Joon KIM, Young Seon SON, Su Jin SHIN, Jae Young AHN, Ju Mi YUN, HanMei CHOI
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Patent number: 9530899Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.Type: GrantFiled: September 2, 2014Date of Patent: December 27, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bi O Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
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Patent number: 9514926Abstract: Embodiments of the disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.Type: GrantFiled: May 4, 2015Date of Patent: December 6, 2016Assignee: SEOUL VIOSYS CO., LTD.Inventors: Su Youn Hong, Joo Won Choi, Jeong Hun Heo, Su Jin Shin, Choong Min Lee
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Patent number: 9450141Abstract: Disclosed are a method for separating a growth substrate, a method for manufacturing a light-emitting diode, and the light-emitting diode. The method for separating a growth substrate, according to one embodiment, comprises: preparing a growth substrate; forming a sacrificial layer and a mask pattern on the growth substrate; etching the sacrificial layer by using electrochemical etching (ECE); covering the mask pattern, and forming a plurality of nitride semiconductor stacking structures which are separated from each other by an element separation area; attaching a support substrate to the plurality of semiconductor stacking structures, wherein the support substrate has a plurality of through-holes connected to the element separation area; and separating the growth substrate from the nitride semiconductor stacking structures.Type: GrantFiled: August 1, 2013Date of Patent: September 20, 2016Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Young Wug Kim, Su Jin Shin, Su Youn Hong
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Publication number: 20160172539Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.Type: ApplicationFiled: February 10, 2016Publication date: June 16, 2016Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Su Jin Shin, Ki Bum Nam, Yu Dae Han, A Ram Cha Lee
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Publication number: 20160133643Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: ApplicationFiled: January 14, 2016Publication date: May 12, 2016Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Patent number: 9263255Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.Type: GrantFiled: March 19, 2013Date of Patent: February 16, 2016Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Su Jin Shin, Ki Bum Nam, Yu Dae Han, A Ram Cha Lee
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Patent number: 9257573Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.Type: GrantFiled: July 24, 2013Date of Patent: February 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hoon Choi, Dong-Kyum Kim, Jin-Gyun Kim, Su-Jin Shin, Sang-Hoon Lee, Ki-Hyun Hwang
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Publication number: 20150380236Abstract: Embodiments of the disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.Type: ApplicationFiled: May 4, 2015Publication date: December 31, 2015Inventors: Su Youn Hong, Joo Won Choi, Jeong Hun Heo, Su Jin Shin, Choong Min Lee
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Patent number: 9184172Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.Type: GrantFiled: December 12, 2014Date of Patent: November 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Seok-Hoon Kim, Su-Jin Shin, Woo-Sung Lee, Tae-Ouk Kwon
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Publication number: 20150318436Abstract: Disclosed are a method for separating a growth substrate, a method for manufacturing a light-emitting diode, and the light-emitting diode. The method for separating a growth substrate, according to one embodiment, comprises: preparing a growth substrate; forming a sacrificial layer and a mask pattern on the growth substrate; etching the sacrificial layer by using electrochemical etching (ECE); covering the mask pattern, and forming a plurality of nitride semiconductor stacking structures which are separated from each other by an element separation area; attaching a support substrate to the plurality of semiconductor stacking structures, wherein the support substrate has a plurality of through-holes connected to the element separation area; and separating the growth substrate from the nitride semiconductor stacking structures.Type: ApplicationFiled: August 1, 2013Publication date: November 5, 2015Applicant: Seoul Viosys Co., Ltd.Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Young Wug Kim, Su Jin Shin, Su Youn Hong
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Patent number: 9048086Abstract: Exemplary embodiments of the present disclosure relate to a substrate recycling method and a recycled substrate. The method includes separating a first surface of a substrate from an epitaxial layer; forming a protective layer on an opposing second surface of the substrate; electrochemically etching the first surface of the substrate; and chemically etching the electrochemically etched first surface of the substrate.Type: GrantFiled: April 29, 2014Date of Patent: June 2, 2015Assignee: Seoul Viosys Co., Ltd.Inventors: Su Youn Hong, Joo Won Choi, Jeong Hun Heo, Su Jin Shin, Choong Min Lee