Abstract: A memory device having a plurality of memory blocks compensates for a characteristic change of a memory cell due to stopping an erase operation. The memory device also includes a voltage generator configured to generate voltages used by the memory device in performing an erase operation on a selected memory block among the plurality of memory blocks. The memory device further includes an erase stop controller configured to control stopping and resuming the erase operation, and counting the number of times the erase operation is stopped to generate a stop count value when the erase operation is stopped. The memory device additionally includes a count value storage configured to store and output the stop count value.

Abstract: A memory device having a plurality of memory blocks compensates for a characteristic change of a memory cell due to stopping an erase operation. The memory device also includes a voltage generator configured to generate voltages used by the memory device in performing an erase operation on a selected memory block among the plurality of memory blocks. The memory device further includes an erase stop controller configured to control stopping and resuming the erase operation, and counting the number of times the erase operation is stopped to generate a stop count value when the erase is stopped. The memory device additionally includes a count value storage configured to store and output the stop count value.

Abstract: This application relates to a digital live book production system for converting the contents of a book into multimedia contents, thus enabling a user to learn the contents of the book quickly and in an interesting way. In one aspect, the digital live book production system includes a book input unit to which sentences of a book are input and an image generation unit configured to generate images corresponding to contents of the sentences input to the book input unit. The system may also include an image alignment unit configured to arrange the images in one screen frame according to the contents of the sentences. The system may further include a screen frame arrangement unit configured to select some screen frames and connect the selected screen frames according to a story of a book, to generate a digital live book.

Abstract: A memory device includes a memory cell array including a plurality of blocks, a power supply unit suitable for generating at least one erase voltage and supplying the at least one erase voltage to the memory cell array, a control logic suitable for receiving multi-block erase information for the same plane, sequentially transmitting block address information included in the multi-block erase information to the row decoder, and outputting an erase control signal to the power supply unit when a last block address information is transmitted, and a row decoder suitable for decoding the block addresses and selecting an erase block of the memory cell array.

Abstract: There are provided an electronic device, and more particularly, to a memory system capable of detecting transmission errors and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes generating reception count information by counting a number of bits of a predetermined value of data received from the semiconductor memory device, requesting the semiconductor memory device to transmit transmission count information representing a number of bits of the predetermined value of the data transmitted by the semiconductor memory device and determining whether transmission errors are included in the received data based on the reception count information and the transmission count information.

Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.

Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.