Abstract: A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal.

Abstract: A shift register minimizing bias stress applied to transistors is disclosed.

Abstract: A liquid crystal display device includes a plurality of pixel electrodes to which a data voltage is supplied, a plurality of common electrodes arranged to form electric fields with the pixel electrodes, a plurality of common wire lines commonly connected to the common electrodes in each horizontal line, a plurality of common voltage drive circuits to supply a common voltage to each of the corresponding common wire lines, and a controller for generating clock signals to control the common voltage drive circuits to invert an electric potential of the common voltage to be output from each of the common voltage drive circuits for each frame period.

Abstract: An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.

Abstract: Disclosed herein are a liquid crystal display device, in which a bi-directional internal gate drive circuit is used to cut the number of data lines in half, and a method of driving such liquid crystal display devices. The liquid crystal device includes a pixel array having a plurality of pixels on a lower substrate. The pixels are configured such that two pixels horizontally adjacent to each other are paired to share the same data line. First and second gate drive circuits are housed in the left and right sides of the lower substrate so as to be independently operated in the left and right side of the pixel array. The first gate drive circuit is formed of first to nth odd shift registers, and the second gate drive circuit is formed of first to nth even shift registers.

Abstract: A built-in gate driver having an improved reliability and a display device having the same are provided. A transistor controlled by an output signal of a next stage is further provided and thus a node (Q) is rapidly discharged. Accordingly, the multi-output signals due to the reduced discharge of the node (Q) caused by the degradation of the transistor controlled by a node QB can be prevented. By including only one transistor for controlling the charge of the start pulse signal on the node (Q), it is possible to prevent a malfunction from occurring when the transistor connected to the clock is degraded by the periodic clock of a high state. Also, an image quality and the reliability of the gate driver can be improved.

Abstract: A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal.

Abstract: An output buffer in each stage of a shift register applies a first clock signal to an output line under control of a first node and a second driving voltage to the output line under control of second and third nodes. A first node controller controls the first node using a start pulse and an output signal of the next stage. A second node controller selectively applies a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals. A third node controller applies the voltage at the fourth node and the second driving voltage to the third node opposite to the second node. A fourth node controller controls the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.

Abstract: A shift register having an amorphous silicon thin film transistor for decreasing a distortion of the output signal is disclosed. In the shift register having a plurality of stages for shifting an input signal using first and second driving voltages, first and second clock signals and a start pulse, each of said plurality of stages includes an output buffer for selectively applying any one of the first and second clock signals and the second driving voltage to an output line under control of first and second nodes; a pre-charger for pre-charging the first driving voltage into the first node in response to said start pulse; a second node controller for selectively supplying the first and second driving voltages to the second node in such a manner to be opposite to the first node using said start pulse and an output signal of the next stage; and a first node controller for supplying the second driving voltage to the first node in a time interval excluding the time interval for said pre-charging.

Abstract: A liquid crystal display device includes a liquid crystal display panel having an effective area and a non-display area, and a temperature sense pattern provided within the non-display area of the liquid crystal display panel.

Abstract: It is an object of the present invention to provide a LOG-type liquid crystal display panel and a fabricating method that is adaptive for reducing a line resistance of a LOG-type signal line group within the confined area. A LOG-type liquid crystal display panel according to one aspect of the present invention includes a picture display part having a plurality of liquid crystal cells, each of which is arranged at each intersection area between gate lines and data lines; and line on glass type signal lines, being provided at an outer area of the picture display part by a line on glass system, for applying driving signals required for drive integrated circuits for driving the gate lines and the data lines, wherein said any one signal line of the line on glass type signal lines is provided by different metal layers formed between the insulating films and connected with each other in parallel.