Abstract: In a method for fabricating a magnetic tunnel junction, a fixed layer, a tunnel insulating layer, a free layer, and an anti-etch layer are formed on a substrate. A sacrificial layer having a hole is formed on the anti-etch layer. An upper electrode is buried in the hole. The sacrificial layer is removed. The anti-etch layer, the free layer, the tunnel insulating layer, and the fixed layer are etched using the upper electrode as a mask.

Abstract: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.

Abstract: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.

Abstract: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.

Abstract: A resistive memory device includes: a substrate, an insulation layer arranged over the substrate, a first electrode plug penetrating the insulation layer from the substrate, having a portion protruded out of an upper portion of the insulation layer, and having peaks at edges of the protruded portion, a resistive layer disposed over the insulation layer and covering the first electrode plug, and a second electrode arranged over the resistive layer.

Abstract: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

Abstract: Disclosed herein is a semiconductor device having an enhanced floating body and a fabrication method for increasing operational stability of the device. The method includes depositing a fin structure on a silicon-on-insulator, forming a gate pattern covering the fin structure, and forming conductive regions in the silicon-on-insulator exposed at both sides of the gate pattern to compartmentalize a floating body of each transistor.

Abstract: A fuse box of a semiconductor device includes a plurality of metal fuses formed on a first interlayer dielectric of a semiconductor substrate and previously removed in blowing regions thereof; a conductive oxidation layer formed to cover removed blowing regions of the metal fuses; a second interlayer dielectric formed on the first interlayer dielectric including the conductive oxide layer; and a plurality of plugs formed in the second interlayer dielectric to be brought into contact with the metal fuses which are removed in the blowing regions thereof.

Abstract: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

Abstract: A resistive memory device includes: a substrate, an insulation layer arranged over the substrate, a first electrode plug penetrating the insulation layer from the substrate, having a portion protruded out of an upper portion of the insulation layer, and having peaks at edges of the protruded portion, a resistive layer disposed over the insulation layer and covering the first electrode plug, and a second electrode arranged over the resistive layer.

Abstract: A method for fabricating a semiconductor device comprises: forming a gate pattern over a silicon active region and an insulating layer, which form a semiconductor substrate; removing the silicon active region exposed between the gate patterns; and filling a space between the gate patterns to form a plug.

Abstract: A method for manufacturing a semiconductor device that has a floating body transistor may include: etching a SOI substrate to expose a BOX region, epitaxially growing sidewalls of the substrate and contacting the grown silicon to a landing plug poly to form source/drain regions. The method reduces the occurrence of a punch-through phenomenon between the source and the drain without decreasing the thickness of the SOI substrate, and also facilitates junction isolation.

Abstract: A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

Abstract: A fuse box of a semiconductor device includes a plurality of metal fuses formed on a first interlayer dielectric of a semiconductor substrate and previously removed in blowing regions thereof; a conductive oxidation layer formed to cover removed blowing regions of the metal fuses; a second interlayer dielectric formed on the first interlayer dielectric including the conductive oxide layer; and a plurality of plugs formed in the second interlayer dielectric to be brought into contact with the metal fuses which are removed in the blowing regions thereof.

Abstract: A method for fabricating a semiconductor device, wherein a multi-layered hard mask layer having a stacked structure of nitride film/oxide film/nitride film is disclosed. The method for fabricating a semiconductor device comprises the steps of: forming a gate insulating film and a conductive layer for gate electrode; forming a multi-layered hard mask layer on the conductive layer, wherein each layer of the multi-layered hard mask layer is formed of materials different from one another; etching the structure to form a stacked structure of a gate insulating film pattern, a gate electrode and a hard mask layer pattern; forming an insulating film spacer; forming an interlayer insulating film on the entire surface; etching the interlayer insulating film to form a landing plug contact hole; forming a conductive layer for landing plug on the entire surface; and planarizing the conductive layer for a landing plug to form a landing plug.

Abstract: A method for fabricating a semiconductor device, wherein a multi-layered hard mask layer having a stacked structure of nitride film/oxide film/nitride film is disclosed. The method for fabricating a semiconductor device comprises the steps of: forming a gate insulating film and a conductive layer for gate electrode; forming a multi-layered hard mask layer on the conductive layer, wherein each layer of the multi-layered hard mask layer is formed of materials different from one another; etching the structure to form a stacked structure of a gate insulating film pattern, a gate electrode and a hard mask layer pattern; forming an insulating film spacer; forming an interlayer insulating film on the entire surface; etching the interlayer insulating film to form a landing plug contact hole; forming a conductive layer for landing plug on the entire surface; and planarizing the conductive layer for a landing plug to form a landing plug.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is formed in a cell region of a semiconductor substrate before a source/drain region is formed in a peripheral circuit region of the semiconductor substrate using an epitaxially grown silicon film in a high temperature process, to obtain a contact plug having a high filling characteristic and a low contact resistance. In addition, additional ion-implantation process of a P type impurity in the subsequent bit line contact formation can be omitted to simplify the fabrication process. The method is suitable for the high speed merged DRAM logic process to achieve the high speed operation of the semiconductor device, and improves a process yield and reliability of the semiconductor device.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is formed in a cell region of a semiconductor substrate before a source/drain region is formed in a peripheral circuit region of the semiconductor substrate using an epitaxially grown silicon film in a high temperature process, to obtain a contact plug having a high filling characteristic and a low contact resistance. In addition, additional ion-implantation process of a P type impurity in the subsequent bit line contact formation can be omitted to simplify the fabrication process. The method is suitable for the high speed merged DRAM logic process to achieve the high speed operation of the semiconductor device, and improves a process yield and reliability of the semiconductor device.