Patents by Inventor Su-Ping Chiu

Su-Ping Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating interconnection in an insulating layer on a wafer
    Patent number: 7253093
    Abstract: A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
    Type: Grant
    Filed: February 5, 2005
    Date of Patent: August 7, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Steven G S Lin, Su-Ping Chiu
  • INTERCONNECTION IN AN INSULATING LAYER ON A WAFER
    Publication number: 20070152216
    Abstract: An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
    Type: Application
    Filed: March 18, 2007
    Publication date: July 5, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Steven Lin, Su-Ping Chiu
  • METHOD FOR FABRICATING INTERCONNECTION IN AN INSULATING LAYER ON A WAFER AND STRUCTURE THEREOF
    Publication number: 20060178001
    Abstract: A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
    Type: Application
    Filed: February 5, 2005
    Publication date: August 10, 2006
    Inventors: Steven GS Lin, Su-Ping Chiu