Patents by Inventor Su-Ping Teong

Su-Ping Teong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7363236
    Abstract: A method, apparatus and system are provided for determining the price of a reticle set. The system retrieves information related to a specific reticle set from various data sources (e.g., data bases) and determines a price for the reticle set. An example embodiment of the method of the invention for calculating a price of a reticle set comprises: a) receiving customer information for the reticle set and storing the customer information; b) receiving sales order data for the reticle set and storing the sales order data; c) retrieving layer information for the reticle set and storing the layer information; d) retrieving cost data for the layer information for the reticle set and storing the cost data; e) determining the price of the reticle set using the layer information, the sales order data, and the cost data; and storing the price of the reticle set; and f) outputting the price of the reticle set.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: April 22, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Danchai Kochpatcharin, Jennifer Su Ping Teong, Yee Hwee Phuan, Elizabeth Lim, Kenneth Zoo Khean Ngeow, Winson Yong
  • Patent number: 6876080
    Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: April 5, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Su-Ping Teong
  • Publication number: 20040181458
    Abstract: A method, apparatus and system are provided for determining the price of a reticle set. The system retrieves information related to a specific reticle set from various data sources (e.g., data bases) and determines a price for the reticle set.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 16, 2004
    Inventors: Danchai Kochpatcharin, Jennifer Su Ping Teong, Yee Hwee Phuan, Elizabeth Lim, Kenneth Zoo Khean Ngeow, Wilson Yong
  • Publication number: 20030071359
    Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 17, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventor: Su-Ping Teong
  • Patent number: 6025634
    Abstract: An integrated circuit having formed therein a low contact leakage and low contact resistance integrated circuit device electrode. The integrated circuit comprises a semiconductor substrate having an isolation region formed upon the semiconductor substrate. The isolation region bounds an active region of the semiconductor substrate adjoining the isolation region. There is formed at least in part within the active region of the semiconductor substrate an integrated circuit device. The integrated circuit device has an integrated circuit device electrode formed within a portion of the active region of the semiconductor substrate bounded by the isolation region. The integrated circuit also comprises a patterned metal silicide layer aligned upon the integrated circuit device electrode.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: February 15, 2000
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Su Ping Teong
  • Patent number: 5693563
    Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: December 2, 1997
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd.
    Inventor: Su-Ping Teong
  • Patent number: 5661085
    Abstract: A method for forming a low contact leakage and low contact resistance integrated circuit device electrode within an integrated circuit, and the low contact leakage and low contact resistance integrated circuit device electrode formed through the method. There is first formed within a semiconductor substrate an integrated circuit device electrode. The integrated circuit device electrode has a width upon the semiconductor substrate of less than the width of a conductor element desired to be formed upon the integrated circuit device electrode plus two times the registration tolerance of a fabrication tool employed in defining the location of the conductor element desired to be formed upon the integrated circuit device electrode. Formed then upon the semiconductor substrate including the integrated circuit device electrode is a blanket metal silicide forming metal layer.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: August 26, 1997
    Assignee: Chartered Semiconductor Manufacturing Pte, Ltd.
    Inventor: Su Ping Teong
  • Patent number: 5639692
    Abstract: A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: June 17, 1997
    Assignee: Chartered Semiconductor Manufacturing Pte, Ltd.
    Inventor: Jennifer Su Ping Teong