Abstract: A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

Abstract: A method of wafer stacking packaging. The method comprises providing a die array including a plurality of singulated first dies cut from a first wafer; providing a second wafer with inseparate the second dies and an adhesive layer on an active surface thereof; pre-cutting the second wafer to a specified depth from the active surface thereof; stacking the active surface of second wafer onto a backside of the first dies, wherein each of the second dies only stack on one of the first dies; thinning the second wafer from the backside thereof to form a plurality of singulated the second dies stacked on the first dies simultaneously.

Abstract: A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. -The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A semiconductor package comprises a first chip, a substrate, a middle layer, a second chip, and an encapsulant. The first chip has an active surface and a high-frequency element defining a high-frequency area on the active surface. The substrate supports the first chip and is electrically connected to the first chip. The middle layer is disposed on the first chip and has a recess corresponding to the high-frequency area. The second chip is disposed on the middle layer and electrically connected to either the first chip or the substrate. The encapsulant encapsulates the first chip, the middle layer, the second chip, and a part of the substrate.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate. The present invention further provides a method for manufacturing the semiconductor chip package.

Abstract: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. A molding compound is formed to cover the semiconductor chip, the substrate, the top surface and the bottom surface of the stiffener. Afterwards, a singulation step is performed to cut the molding compound, the substrate and the stiffener.

Abstract: A process for sawing a substrate strip marks corresponding to substrate areas of substrate strips which are arranged side-by-side on a plate. A saw machine is mechanically moved to the substrate areas and positioned by the alignment marks of corresponding substrate areas for cutting the substrate areas of the substrate strips in the first phase. Then the saw machine is further mechanically moved to the substrate areas again and is positioned by the alignment marks of corresponding substrate areas again for cutting the substrate areas of the substrate strips in the second phase. Therefore, an error in any of the substrate areas in the first phase and second phase will not accumulate to the subsequent substrate areas in the substrate strip.

Abstract: A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.

Abstract: The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A leadless semiconductor package disposed on a substrate includes a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

Abstract: A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract: A thermal enhance package mainly comprises a chip, a substrate unit, a heat spreader unit and a plurality of pellets. The chip is disposed above the substrate unit and electrically connected to the substrate unit, and an encapsulation unit encapsulates the chip, the substrate unit, the heat spreader unit and the pellets. Therein the pellets are formed on the substrate unit and connect the substrate unit and the heat spreader unit. Thus the heat arisen out of the chip can be transmitted to the heat spreader unit not only through the encapsulation unit but also the pellets. Moreover, the substrate unit has at least one grounding contact connecting to one of the pellets so as to provide the thermal enhance package a good shielding. In addition, a method for manufacturing the thermal enhance package is also provided.