Patents by Inventor Su-Ya Lin

Su-Ya Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for automatically modifying integrated circuit layout
    Patent number: 7496862
    Abstract: This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: February 24, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mi-Chang Chang, Su-Ya Lin, Jen-Hang Yang, Li-Chun Tien
  • Method for automatically modifying integrated circuit layout
    Publication number: 20080059916
    Abstract: This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 6, 2008
    Inventors: Mi-Chang Chang, Su-Ya Lin, Jen-Hang Yang, Li-Chun Tien