Abstract: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

Abstract: A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: A method and system that can display information about messages that are not stored because sufficient space to store a message does not exist in a mobile communication terminal are provided. A method of displaying message information using a message server and mobile communication terminal includes storing at least two messages in the message server, generating a message including message information from the stored messages, transmitting the message to the mobile communication terminal, and acquiring and displaying the message information from the message.

Abstract: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

Abstract: A magnetic random access memory device includes a digit line, a bit line, and a magnetic memory cell disposed in an intersection between the digit line and the bit line. The digit line is extended in a first direction on a substrate. The bit line is extended in a second direction on the substrate. The magnetic memory cell includes a rectangular free magnetic layer magnetized in a direction according to an externally applied magnetic field. A major axis of the rectangular free magnetic layer is substantially parallel to the first direction, and a minor axis of the rectangular free magnetic layer is substantially parallel to the second direction. Thus, multiple input/output program (write) operations and multiple input/output repair operations may be effectively performed.

Abstract: A magnetic memory device includes a memory cell array block and a reference memory cell array block having a plurality of magnetic memory cells arranged, respectively, at intersections of wordlines, digit lines, and bitlines, and reference wordlines, the digit lines, and a reference bitline, a first bitline clamp circuit coupled to a bitline to which a first selected magnetic memory cell is connected and supplying a first current to the first selected magnetic memory cell through the bitline, second and third bitline clamp circuits coupled to respective upper and lower ends of the reference bitline, for supplying a second current to selected magnetic memory cells in the reference memory cell array block through the reference bitline, and a sense amplifier for sensing and amplifying currents on first and second data lines, respectively connected to the bitline and the reference bitline, to judge data of the first selected magnetic memory cell.

Abstract: A magnetic random access memory device includes a digit line, a bit line, and a magnetic memory cell disposed in an intersection between the digit line and the bit line. The digit line is extended in a first direction on a substrate. The bit line is extended in a second direction on the substrate. The magnetic memory cell includes a rectangular free magnetic layer magnetized in a direction according to an externally applied magnetic field. A major axis of the rectangular free magnetic layer is substantially parallel to the first direction, and a minor axis of the rectangular free magnetic layer is substantially parallel to the second direction. Thus, multiple input/output program (write) operations and multiple input/output repair operations may be effectively performed.

Abstract: A magnetic memory device includes a memory cell array block and a reference memory cell array block having a plurality of magnetic memory cells arranged, respectively, at intersections of wordlines, digit lines, and bitlines, and reference wordlines, the digit lines, and a reference bitline, a first bitline clamp circuit coupled to a bitline to which a first selected magnetic memory cell is connected and supplying a first current to the first selected magnetic memory cell through the bitline, second and third bitline clamp circuits coupled to respective upper and lower ends of the reference bitline, for supplying a second current to selected magnetic memory cells in the reference memory cell array block through the reference bitline, and a sense amplifier for sensing and amplifying currents on first and second data lines, respectively connected to the bitline and the reference bitline, to judge data of the first selected magnetic memory cell.