Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.