Patents by Inventor Su-Yun Kim
Su-Yun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150378Abstract: The present disclosure provides a novel compound represented by the following Chemical Formula 1 and an organic light emitting device including the same: wherein R1 to R8 are described herein.Type: ApplicationFiled: March 31, 2022Publication date: May 9, 2024Applicant: LG Chem, Ltd.Inventors: Young Kwang Kim, Jaechol Lee, Yongwook Kim, Soyoung Yu, Shin Sung Kim, Byeong Yun Lim, Su Hun Jeong
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Publication number: 20240069535Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.Type: ApplicationFiled: July 14, 2022Publication date: February 29, 2024Inventors: Shinkyu KANG, Min Yong KIM, Youngduk KIM, Nam Hyuck KIM, Su Ho JEON, Min Hee KWON, Sung Nam CHO, Hyeong Geun CHAE, Gyeong Yun JO, Moon Kyu JO, Kyungchul HWANG, Moo Hyun YOO, Han Seung KIM, Daewoon JUNG, Seungtae KIM, Junhyeok JEON
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Patent number: 11912109Abstract: A flush glass apparatus includes a fixed glass having an opening, an operation glass configured to open and close the opening of the fixed glass, a lower rail configured to slidably support a lower portion of the operation glass, a sealing member provided below the lower rail to seal a gap between an inner surface of the fixed glass and a vehicle body, one or more upper drain holes provided on the lower rail to discharge rainwater on the lower rail to a buffer area between the lower rail and the sealing member, and a drain induction member interposed between the inner surface of the fixed glass and the sealing member and providing a lower drain hole to discharge rainwater in the buffer area to the outside.Type: GrantFiled: September 29, 2020Date of Patent: February 27, 2024Assignees: Hyundai Motor Company, Kia Motors Corporation, Webasto Korea Holdings Ltd.Inventors: Jeong Hyeon Kim, Seong Min Gwak, Su Yun Choi
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Patent number: 11476211Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.Type: GrantFiled: December 15, 2020Date of Patent: October 18, 2022Assignee: NEPES CO., LTD.Inventors: Jun Kyu Lee, Su Yun Kim, Dong Hoon Oh, Yong Tae Kwon, Ju Hyun Nam
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Publication number: 20220278053Abstract: A technical idea of the present disclosure provides a semiconductor package, as a semiconductor package mounted on a circuit board, including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.Type: ApplicationFiled: March 24, 2020Publication date: September 1, 2022Applicant: NEPES CO., LTD.Inventors: Ju Hyun NAM, Jun Kyu LEE, Yong Tae KWON, Su Yun KIM, Dong Hoon OH
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Patent number: 11393768Abstract: A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.Type: GrantFiled: September 21, 2020Date of Patent: July 19, 2022Assignee: NEPES CO., LTD.Inventors: Dong Hoon Oh, Su Yun Kim, Ju Hyun Nam
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Publication number: 20210398869Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.Type: ApplicationFiled: October 17, 2019Publication date: December 23, 2021Applicant: NEPES CO., LTD.Inventors: Su Yun KIM, Dong Hoon OH, Yong Tae KWON, Jun Kyu LEE, Kyeong Rok SHIN, Yong Woon YEO
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Publication number: 20210343656Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.Type: ApplicationFiled: September 26, 2019Publication date: November 4, 2021Applicant: Nepes Co., Ltd.Inventors: Yong Tae KWON, Jun Kyu Lee, Dong Hoon OH, Su Yun KIM, Kyeong Rok SHIN
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Publication number: 20210193602Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.Type: ApplicationFiled: December 15, 2020Publication date: June 24, 2021Applicant: Nepes CO., LTD.Inventors: Jun Kyu LEE, Su Yun Kim, Dong Hoon OH, Yong Tae KWON, Ju Hyun NAM
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Publication number: 20210091008Abstract: A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.Type: ApplicationFiled: September 21, 2020Publication date: March 25, 2021Applicant: Nepes CO., LTD.Inventors: Dong Hoon Oh, Su Yun Kim, Ju Hyun Nam
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Publication number: 20210060573Abstract: A conveying screw for a food waste disposal device that can stir, crush and cut food waste generated from homes or restaurants, while transferring the food waste, to reduce the amount of the food waste, includes a rotational shaft, and a plurality of spiral rotor blades installed to an outer peripheral surface of the rotational shaft in a spiral pattern to stir, crush and cut food waste. Each of the rotor blades is provided with a plurality of air supply holes penetrating the rotor blade to supply external air to the food waste between the opposite rotor blades, thereby generating bubbles from the food waste and then discharging vapor.Type: ApplicationFiled: September 6, 2018Publication date: March 4, 2021Inventor: Su Yun KIM
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Publication number: 20030064365Abstract: The present invention provides a method for detecting heterozygous mutation using E. coli stop codon assay. The present invention further provides a gap vector used in the E. coli stop codon assay. According to this invention, the heterozygous mutation in certain gene, e.g. APC gene or BRCA1 gene, may be detected in simple and rapid manner, for example, visual observation on colonies.Type: ApplicationFiled: June 26, 2001Publication date: April 3, 2003Inventors: Young-Ho Moon, Hye-Jung Nam, Dong-Hwan Kim, Hyun-Pil Cho, Su-Mi Han, Mi-Uk Chin, Seg-Ho Choi, Su-Yun Kim, Sang-Yong Choi, Byung-Joo Song, Eun-Ryoung Kim, Hyo-Jong Kim, Il-Soo Kim