Patents by Inventor Sualp Aras
Sualp Aras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973499Abstract: A bidirectional level shifter circuit includes first and second driver circuits, first and second comparators, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first reference input, and a first comparator input that is coupled to the second driver output. The second comparator includes a second comparator output, a second reference input, and a second comparator input is coupled to the first driver output. The control circuit includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.Type: GrantFiled: November 29, 2022Date of Patent: April 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Deric Wayne Waters, Roland Son, Sualp Aras, Ralph Braxton Wade, III
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Patent number: 11574902Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.Type: GrantFiled: January 31, 2019Date of Patent: February 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eung Jung Kim, Kyle Clifton Schulmeyer, Sualp Aras, Md Abidur Rahman, Xiaochun Zhao
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Patent number: 11467192Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: GrantFiled: October 13, 2020Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Patent number: 11218147Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.Type: GrantFiled: September 11, 2020Date of Patent: January 4, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Md. Abidur Rahman, Adam Quirk, Stephen Nortman, Sualp Aras
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Patent number: 11184000Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.Type: GrantFiled: June 6, 2018Date of Patent: November 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eung Jung Kim, Sualp Aras, Abidur Rahman
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Publication number: 20210025925Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Publication number: 20200412355Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Inventors: Md. Abidur Rahman, Adam Quirk, Stephen Nortman, Sualp Aras
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Patent number: 10837986Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: GrantFiled: February 6, 2020Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Patent number: 10812063Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.Type: GrantFiled: March 4, 2019Date of Patent: October 20, 2020Assignee: Texas Instruments IncorporatedInventors: Md. Abidur Rahman, Adam Quirk, Stephen Nortman, Sualp Aras
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Publication number: 20200251465Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Inventors: EUNG JUNG KIM, KYLE CLIFTON SCHULMEYER, SUALP ARAS, MD ABIDUR RAHMAN, XIAOCHUN ZHAO
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Publication number: 20200174045Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Patent number: 10670638Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: GrantFiled: April 6, 2018Date of Patent: June 2, 2020Assignee: Texas Instruments IncorporatedInventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Patent number: 10554203Abstract: In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.Type: GrantFiled: November 30, 2018Date of Patent: February 4, 2020Assignee: Texas Instruments IncorporatedInventors: Sualp Aras, Eung Jung Kim, Abidur Md Rahman
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Patent number: 10404056Abstract: A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.Type: GrantFiled: August 1, 2016Date of Patent: September 3, 2019Assignee: Texas Instruments IncorporatedInventors: Sualp Aras, Adam Quirk, Md. Abidur Rahman
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Patent number: 10386876Abstract: A circuit protective system. The system has: (i) an input for sensing an operational voltage responsive to a current flowing through a transistor; (ii) circuitry for applying a forced voltage at the input; (iii) voltage-to-current conversion circuitry for outputting a reference current in response to the forced voltage at the input; (iv) circuitry for providing a reference trim current in response to a trim indicator; and (v) comparison circuitry for outputting a limit signal in response to a comparison of the reference current and the reference trim current.Type: GrantFiled: August 8, 2016Date of Patent: August 20, 2019Assignee: Texas Instruments IncorporatedInventors: Md. Abidur Rahman, Sualp Aras, Tri Cao Nguyen
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Publication number: 20190214980Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.Type: ApplicationFiled: June 6, 2018Publication date: July 11, 2019Inventors: Eung Jung Kim, Sualp Aras, Abidur Rahman
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Publication number: 20190199341Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.Type: ApplicationFiled: March 4, 2019Publication date: June 27, 2019Inventors: Md. Abidur Rahman, Adam Quirk, Stephen Nortman, Sualp Aras
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Patent number: 10326268Abstract: A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.Type: GrantFiled: August 1, 2016Date of Patent: June 18, 2019Assignee: Texas Instruments IncorporatedInventors: Eung J. Kim, Md. Abidur Rahman, Sualp Aras
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Publication number: 20190137546Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.Type: ApplicationFiled: April 6, 2018Publication date: May 9, 2019Applicant: Texas Instruments IncorporatedInventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
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Patent number: 10284191Abstract: A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.Type: GrantFiled: August 1, 2016Date of Patent: May 7, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Md. Abidur Rahman, Adam Quirk, Stephen Nortman, Sualp Aras