Abstract: A method of making a multilayered circuitized substrate in which a continuous process is used to form electrically conductive layers which each will form part of a sub-composite. The sub-composites are then aligned such that openings within the conductive layers are also aligned, the sub-composites are then bonded together, and a plurality of holes are then laser drilled through the entire thickness of the bonded structure. The dielectric layers used in the sub-composites do not include continuous or semi-continuous fibers therein, thus expediting hole formation there-through.

Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.