Patents by Inventor SUBAS BASTOLA

SUBAS BASTOLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11632130
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Publication number: 20220255559
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 11, 2022
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Patent number: 11283466
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Patent number: 11043965
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Publication number: 20200067526
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: September 6, 2019
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Publication number: 20180191374
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: December 22, 2017
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Publication number: 20170163286
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: December 26, 2013
    Publication date: June 8, 2017
    Inventors: Zuoguo WU, Debendra DAS SHARMA, Md. Mohiuddin MAZUMDER, Subas BASTOLA, Kai XIAO
  • Publication number: 20170085243
    Abstract: One embodiment provides an apparatus. The apparatus includes an impedance matching interconnect having a first end and a second end. The impedance matching interconnect includes an interface trace having a first width at the first end and a second width at the second end, the first width less than the second width. The impedance matching interconnect further includes a first dielectric layer adjacent the interface trace; a first reference plane adjacent the first dielectric layer; at least one via adjacent the first reference plane; and a second reference plane adjacent the at least one via, the at least one via to couple the first reference plane and the second reference plane. A first distance between the interface trace and the first reference plane is less than a second distance between the interface trace and the second reference plane.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Applicant: Intel Corporation
    Inventors: BEOM-TAEK LEE, DHANYA ATHREYA, KEMAL AYGUN, SUBAS BASTOLA