Patents by Inventor Subba Reddy Kallam
Subba Reddy Kallam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210072906Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: ApplicationFiled: August 13, 2020Publication date: March 11, 2021Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkata Siva Prasad PULAGAM, Anusha BIYYANI, Venkatesh VINJAMURI, Shahabuddin MOHAMMED, Rahul Kumar GURRAM, Akhil SONI
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Publication number: 20210072813Abstract: A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.Type: ApplicationFiled: August 29, 2020Publication date: March 11, 2021Applicant: Silicon Laboratories Inc.Inventors: Partha Sarathy MURALI, Subba Reddy KALLAM, Venkat MATTELA
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Publication number: 20210076248Abstract: A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.Type: ApplicationFiled: August 2, 2020Publication date: March 11, 2021Applicant: Silicon Laboratories Inc.Inventors: Subba Reddy KALLAM, Partha MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Publication number: 20210072995Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.Type: ApplicationFiled: August 3, 2020Publication date: March 11, 2021Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Publication number: 20210073027Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.Type: ApplicationFiled: August 2, 2020Publication date: March 11, 2021Applicant: Silicon Laboratories Inc.Inventors: Subba Reddy KALLAM, Partha Sarathy MURALI, Venkat MATTELA, Venkata Siva Prasad PULAGAM
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Patent number: 10931301Abstract: A code decompression engine reads compressed code from a memory containing a series of code parts and a dictionary part. The code parts each have a bit indicating compressed or uncompressed. When the code part is compressed, it has a value indicating the number of segments, followed by the segments, followed by an index into the dictionary part. The decompressed instruction is the dictionary value specified by the index, which is modified by the segments. Each segment describes the modification to the dictionary part specified by the index by a mask type, a mask offset, and a mask.Type: GrantFiled: December 16, 2019Date of Patent: February 23, 2021Assignee: Redpine Signals, Inc.Inventors: Subba Reddy Kallam, Sriram Mudulodu
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Publication number: 20200401206Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Venkat MATTELA, Aravinth Kumar Ayyappan, Sairam Regulagadda
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Publication number: 20200396579Abstract: A low power device has a Bluetooth connection and a WLAN interface that can be enabled for high speed communication. The low power device is coupled to an application program running on a remote computer such as a tablet over Bluetooth. When a large amount of data is requested, the high speed WLAN interface is enabled as an Access Point (AP) and data transmitted or received over the low power device AP WLAN interface until the block of data is transferred, after which the WLAN connection is torn down, and the WLAN interface disabled. In this manner, the power consumption during high speed data transfers is minimized.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicant: Redpine Signals, Inc.Inventor: Subba Reddy KALLAM
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Publication number: 20200396681Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.Type: ApplicationFiled: June 14, 2019Publication date: December 17, 2020Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy MURALI, Subba Reddy KALLAM
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Patent number: 10817200Abstract: A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.Type: GrantFiled: October 26, 2017Date of Patent: October 27, 2020Assignee: Silicon Laboratories Inc.Inventors: Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Sailaja Dharani Naga Sankabathula, Venkat Rao Gunturu, Subba Reddy Kallam
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Publication number: 20200336319Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Applicant: Silicon Laboratories Inc.Inventors: Partha Sarathy MURALI, Ajay MANTHA, Nagaraj Reddy ANAKALA, Subba Reddy KALLAM, Venkat MATTELA
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Patent number: 10757652Abstract: A wireless receiver powers up shortly before the expected arrival of a beacon frame, and upon detection of a beacon frame from an access point the station is associated with and determination of subsequent fields of interest, including at least a TIM field, the receiver powers down. At the previously identified fields of interest, the receiver powers up and uses previously stored values to continue packet demodulation, thereafter examining the TIM field to determine whether the AP has packets to transmit to the station.Type: GrantFiled: December 14, 2018Date of Patent: August 25, 2020Assignee: Silicon Laboratories Inc.Inventors: Sriram Mudulodu, Partha Sarathy Murali, SuryaNarayana Varma Nallaparaju, Logeshwaran Vijayan, Subba Reddy Kallam, Venkat Mattela
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Patent number: 10742429Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: GrantFiled: November 14, 2017Date of Patent: August 11, 2020Assignee: Silicon Laboratories Inc.Inventors: Partha Sarathy Murali, Ajay Mantha, Nagaraj Reddy Anakala, Subba Reddy Kallam, Venkat Mattela
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Publication number: 20200133377Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.Type: ApplicationFiled: October 11, 2019Publication date: April 30, 2020Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy MURALI, Suryanarayana Varma NALLAPARAJU, Kriyangbhai Vinodbhai SHAH, Venkata Rao GUNTURU, Subba Reddy KALLAM, Mani Kumar KOTHAMASU
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Publication number: 20200119747Abstract: A code decompression engine reads compressed code from a memory containing a compressed code part and a dictionary part. The compressed code part comprises series of instructions comprising either an uncompressed instruction preceded by an uncompressed code bit, or a compressed instruction comprising a compressed code bit followed by a number of segments field followed by segments, followed by a directory index indication a directory location to read. Each segment consists of a mask type, a mask offset, and a mask.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: Redpine Signals, Inc.Inventors: Subba Reddy KALLAM, Sriram MUDULODU
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Patent number: 10541708Abstract: A code decompression engine reads compressed code from a memory containing a compressed code part and a dictionary part. The compressed code part contains a series of instructions being either an uncompressed instruction preceded by an uncompressed code bit, or a compressed instruction having a compressed code bit followed by a number of segments field followed by segments, followed by a directory index indication a directory location to read. Each segment consists of a mask type, a mask offset, and a mask.Type: GrantFiled: September 24, 2018Date of Patent: January 21, 2020Assignee: Redpine Signals, Inc.Inventors: Subba Reddy Kallam, Sriram Mudulodu
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Publication number: 20190191373Abstract: A wireless receiver powers up shortly before the expected arrival of a beacon frame, and upon detection of a beacon frame from an access point the station is associated with and determination of subsequent fields of interest, including at least a TIM field, the receiver powers down. At the previously identified fields of interest, the receiver powers up and uses previously stored values to continue packet demodulation, thereafter examining the TIM field to determine whether the AP has packets to transmit to the station.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Applicant: REDPINE SIGNALS, INC.Inventors: Sriram MUDULODU, Partha Sarathy MURALI, SuryaNarayana Varma Nallaparaju, Logeshwaran VIJAYAN, Subba Reddy KALLAM, Venkat MATTELA
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Publication number: 20190149343Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy Murali, Ajay MANTHA, Nagaraja Reddy ANAKALA, Subba Reddy KALLAM, Venkat MATTELA
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Publication number: 20190129638Abstract: A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Applicant: Redpine Signals, Inc.Inventors: Partha Sarathy MURALI, Venkata Siva Prasad Pulagam, Sailaja Dharani Naga SANKABATHULA, Venkat Rao Gunturu, Subba Reddy KALLAM
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Patent number: 8245063Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.Type: GrantFiled: June 24, 2008Date of Patent: August 14, 2012Assignee: Redpine Signals, Inc.Inventor: Subba Reddy Kallam