Abstract: A method and apparatus for efficiently controlling the access to a cached shared resource such as dynamic random access memory (DRAM). The access is effected in a pseudo-concurrent manner by two devices such as a central processing unit (CPU) and a bus master agent. While one device accesses data stored in the DRAM, the other device accesses a copy of the DRAM data which is stored in the cache of the shared resource.

Abstract: An execution speed controller for controlling the effective processing rate of a microprocessor including an internal cache memory. In one embodiment, the execution speed controller monitors the activities of the microprocessor to determine when it is executing a section of code whose execution should be slowed. When such a determination is made, the execution speed controller periodically asserts at least one control input to the microprocessor. This periodically prevents the microprocessor from accessing the main memory and the internal cache memory, thereby slowing microprocessor execution. In this embodiment, only those software applications requiring slow down are effected. Newer software applications may not require this mode and may run at full speed. An alternate embodiment that does not require a triggering event is also described. In this embodiment, execution of all software applications is slowed down. This is referred to as the "compatibility" mode.

Abstract: A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is "clean" or "dirty." In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU.

Abstract: A concurrent cache line replacement method and apparatus for a high performance microprocessor system with a write-back cache memory is disclosed. The invention is advantageously utilized in a microprocessor system comprising a CPU, a write back cache memory, DRAM main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer capability. In accordance with the method of operation of the present invention, when a read access by the CPU results in a cache miss to a dirty cache line, the CDC concurrently initiates two operations. The CDC initiates the writing of the dirty line in the cache memory to a write buffer in the DPU, while concurrently, the CDC also initiates the reading of the new line from the DRAM main memory.