Patents by Inventor Subbayyan Venkatsan

Subbayyan Venkatsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for statistical frequency enhancement of statically timed designs
    Patent number: 10318676
    Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 11, 2019
    Assignee: AMPERE COMPUTING LLC
    Inventors: Alfred Yeung, Subbayyan Venkatsan, Hamid Partovi, Vamsi Srikantam
  • TECHNIQUES FOR STATISTICAL FREQUENCY ENHANCEMENT OF STATICALLY TIMED DESIGNS
    Publication number: 20180210987
    Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 26, 2018
    Inventors: Alfred Yeung, Subbayyan Venkatsan, Hamid Partovi, Vamsi Srikantam