Abstract: A method and an apparatus for managing data in a cache memory are described. The method includes determining a frequency of access for each of a plurality of cache lines in a cache memory. Further, the method includes determining an error count for each of the plurality of cache lines. Furthermore, the method includes identifying at least one affected cache line among the plurality of cache lines, based on the frequency of access and the error count. The error count of the at least one affected cache line exceeds a pre-defined threshold value. The method includes identifying at least one target cache line having a least error count. Further, the method includes managing data stored in the at least one affected cache line by swapping the data with the at least one target cache line.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support row-selective self-refresh operation while a host processor is in sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving, from the host device through the channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear probing filter, or a XOR filter. Other aspects and features are also claimed and described.

Abstract: Aspects presented herein may improve the overall performance and efficiency related to recovering a system/subsystem from uncorrectable memory error(s), such as a system/subsystem with resource constraints. For example, an interrupt-based mechanism is provided to handle uncorrectable memory error(s) in a more efficient manner. In one aspect, a device detects an uncorrectable error in memory of a process domain (PD). The device increments an uncorrectable error counter based on detection of the uncorrectable error in the memory. The device performs, based on the uncorrectable error counter, at least one of: (1) triggering a system reset or a subsystem reset if the uncorrectable error counter exceeds a counter threshold, (2) issuing a restart for a set of PDs if the uncorrectable error counter exceeds the counter threshold, or (3) issuing a restart for the PD if the uncorrectable error counter does not exceed the counter threshold.

Abstract: This disclosure provides systems, methods, and devices that support enhanced memory cleaning operations. In a first aspect, a system-on-a-chip (SoC) includes at least one processor and at least one memory coupled to the at least one processor. The at least one processor is configured to cause the SoC to: interrupt a direct memory access (DMA) engine to perform a memory restoration operation on a memory associated with the DMA engine; perform, by a first processor thread, wake-up task operations and quick boot notification operations for a subsystem associated with the memory; perform, by a second processor thread, the memory restoration operation on the memory in parallel with one or more of the wake-up task operations or quick boot notification operations; and perform run time initialization operations for the subsystem based on completion of the wake-up or quick boot operations. Other aspects and features are also claimed and described.

Abstract: Aspects of entry into self-refresh mode by a dynamic random-access memory (DRAM) may be managed using one or more polled registers. Indications of DRAM write activity by the DRAM or a DRAM client may be stored in the registers. The registers may be polled after entry into DRAM self-refresh mode is initiated. The DRAM's entry into self-refresh mode may not be allowed until the registers indicate absence of DRAM write activity.

Abstract: Priority-based restoration of offloaded data back into cache memory in a processor-based system to reduce access misses is disclosed. The processor-based system is configured to offload data from areas of cache memory designated as collapsible, into system memory in response to entering a lower power mode. The processor-based system determines a priority ordering of the offloaded data based on a prediction of its access demand by a processor after exiting the lower power mode. In this manner, when exiting the lower power mode, the processor-based system can restore offloaded data from system memory back into cache memory in such priority ordering. In this manner, the processor can be permitted to perform memory accesses to cache memory before the offloaded data is fully restored as access misses are less likely to occur by restoring data in order of more likely to be accessed sooner after exiting the lower power mode.

Abstract: A system is provided for an SMMU context save process in which only the configuration registers whose contents are changed following an SMMU initialization are saved to a system memory. Similarly, the system performs an SMMU context restore by only writing to the configuration registers whose context had changed prior to the SMMU context save process.

Abstract: Aspects of entry into self-refresh mode by a dynamic random-access memory (DRAM) may be managed using one or more polled registers. Indications of DRAM write activity by the DRAM or a DRAM client may be stored in the registers. The registers may be polled after entry into DRAM self-refresh mode is initiated. The DRAM's entry into self-refresh mode may not be allowed until the registers indicate absence of DRAM write activity.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support row-selective self-refresh operation while a host processor is in sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving, from the host device through the channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear probing filter, or a XOR filter. Other aspects and features are also claimed and described.