Abstract: A system is provided for an SMMU context save process in which only the configuration registers whose contents are changed following an SMMU initialization are saved to a system memory. Similarly, the system performs an SMMU context restore by only writing to the configuration registers whose context had changed prior to the SMMU context save process.

Abstract: Aspects of entry into self-refresh mode by a dynamic random-access memory (DRAM) may be managed using one or more polled registers. Indications of DRAM write activity by the DRAM or a DRAM client may be stored in the registers. The registers may be polled after entry into DRAM self-refresh mode is initiated. The DRAM's entry into self-refresh mode may not be allowed until the registers indicate absence of DRAM write activity.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support row-selective self-refresh operation while a host processor is in sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving, from the host device through the channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear probing filter, or a XOR filter. Other aspects and features are also claimed and described.