Abstract: A network element sends a critical alarm to an element management system, indicating the potential failure of the network element. The network element and critical alarm are verified against existing alarm and identifying information libraries associated with the network element. An incident object including data associated with the critical alarm is generated. A trouble ticket associated with the critical alarm and the network element is then generated, based on the incident object data, in real-time for proactive monitoring of the network and management of the critical alarm at an early stage in order to prevent scaling of a network outage or prevent the outage entirely.

Abstract: Lifecycle Management Testing of a containerized application is conducted by executing a test script by a first containerized application thereby causing an Application Programming Interface (API) call to be issued to at least one automated testing system, running, by the at least one automated testing system, a testing sequence on a second containerized application, different from the first containerized application, based on the API call, and automatically displaying testing sequence results, where the results include an assessment of the health of the second containerized application.

Abstract: A network element sends a critical alarm to an element management system, indicating the potential failure of the network element. The network element and critical alarm are verified against existing alarm and identifying information libraries associated with the network element. An incident object including data associated with the critical alarm is generated. A trouble ticket associated with the critical alarm and the network element is then generated, based on the incident object data, in real-time for proactive monitoring of the network and management of the critical alarm at an early stage in order to prevent scaling of a network outage or prevent the outage entirely.

Abstract: The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

Abstract: The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input.

Abstract: The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input.

Abstract: The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

Abstract: Provided are compositions that include a dielectric matrix material defining multiple voids of substantially uniform respective dimension and configured as a substantially uniform array. The voids may be configured such that charges that accumulate at surfaces of at least some of the voids when the composition is immersed in a uniform external electric field interact with charges that accumulate at surfaces of at least others of the voids to cause movement of the respective charges in a direction having a component transverse to the electric field. Hollow particles may be disposed within respective voids of the array of voids defined by the matrix material, and particles, such as, for example, ceramic, varistor, and/or inorganic dielectric particles, may be incorporated within the matrix material. Associated devices are also provided.