Patents by Inventor Subhash B. Kulkarni
Subhash B. Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080190446Abstract: A “wafer-less” etch chamber cleaning method varies the capacitance applied to radio frequency components of the chuck that is within the etch chamber (varies impedance of the chuck) so as to cause electric field lines within the etch chamber to terminate (bend) away from the chuck. Then the etch chamber can be cleaned using a very aggressive etch chemistry (e.g., NF3) that would otherwise damage the chuck; however, the electric field lines protect the chuck from the etch chemistry. The capacitance is varied according to a pre-established model. Further, the process evaluates the effectiveness of the pre-established model to produce feedback and constantly adjusts the pre-established model to increase the effectiveness of the cleaning process (according to the feedback).Type: ApplicationFiled: February 13, 2007Publication date: August 14, 2008Inventors: Rajiv M. Ranade, Subhash B. Kulkarni, Ole Krogh, Sukesh Patel
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Patent number: 7144769Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: GrantFiled: July 27, 2004Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Patent number: 6821864Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: GrantFiled: March 7, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Patent number: 6809005Abstract: The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: GrantFiled: March 12, 2003Date of Patent: October 26, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Publication number: 20040180510Abstract: The present invention provides methods of producing trench structures having substantially void-free filler materials therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Publication number: 20030170951Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: ApplicationFiled: March 7, 2002Publication date: September 11, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Patent number: 6563173Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: May 16, 2001Date of Patent: May 13, 2003Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 6492684Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: June 11, 2001Date of Patent: December 10, 2002Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Publication number: 20020043686Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: ApplicationFiled: June 11, 2001Publication date: April 18, 2002Inventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Publication number: 20010024863Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: ApplicationFiled: May 16, 2001Publication date: September 27, 2001Inventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 6281095Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: September 4, 1998Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 6133610Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.Type: GrantFiled: January 20, 1998Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Ronald J. Bolam, Subhash B. Kulkarni, Dominic J. Schepis
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Patent number: 5562770Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.Type: GrantFiled: November 22, 1994Date of Patent: October 8, 1996Assignee: International Business Machines CorporationInventors: Bomy A. Chen, Terence B. Hook, Subhash B. Kulkarni
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Patent number: 4504330Abstract: A reduced pressure epitaxial deposition method is disclosed to maximize performance and leakage limited yield of devices formed in the epitaxial layer. The method includes specified prebake and deposition conditions designed to minimize arsenic (buried subcollector) and boron (buried isolation) autodoping effects when pressures below one atmosphere are selected in accordance with the subcollector-to-isolation area ratio.Type: GrantFiled: October 19, 1983Date of Patent: March 12, 1985Assignee: International Business Machines CorporationInventors: Arun K. Gaind, Subhash B. Kulkarni, Michael R. Poponiak