Abstract: Efficient tagging of content items using content embeddings are provided. In one technique, multiple content items are stored a content embedding for content item is stored. Entity names are also stored along with an entity name embedding for each entity name. For each content item, (1) multiple content embeddings that are associated with the content item are identified; (2) a subset of the entity names is identified; and (3) for each entity name in the subset, (i) an embedding of the entity name is identified, (ii) similarity measures are generated based on the entity name embedding and the multiple content embeddings, (iii), a distribution of the similarity measures is generated, (iv) feature values are generated based on the distribution, (v) the feature values are input into a machine-learned classifier, and (vi) based on output from the classifier, it is determined whether to associate the entity name with the content item.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: Present disclosure discloses a simple litz planar architecture using minimal vias for reducing Alternating Current (AC) resistance. The simple litz planar structure comprises a plurality of conductor strands of a first layer, a plurality of conductor strands of a second layer; and a plurality of vias set. The first layer and the second layer are separated by an insulating layer and each vias set is configured to perform transposition between a corresponding conductor strand of the first layer and a conductor strand of the second layer. The disclosed transposition method is simple, easy to manufacture and consequently, cost effective. The reduction in AC resistance obtained using disclosed simple litz planar structure is similar to planar litz winding. Further reduction in AC resistance is obtained by implementing multi-transposition per layer in the disclosed simple litz winding structure.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Abstract: Efficient tagging of content items using content embeddings are provided. In one technique, multiple content items are stored a content embedding for content item is stored. Entity names are also stored along with an entity name embedding for each entity name. For each content item, (1) multiple content embeddings that are associated with the content item are identified; (2) a subset of the entity names is identified; and (3) for each entity name in the subset, (i) an embedding of the entity name is identified, (ii) similarity measures are generated based on the entity name embedding and the multiple content embeddings, (iii), a distribution of the similarity measures is generated, (iv) feature values are generated based on the distribution, (v) the feature values are input into a machine-learned classifier, and (vi) based on output from the classifier, it is determined whether to associate the entity name with the content item.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Abstract: Techniques for efficiently matching two sets of video items are provided. In on technique, an embedding is generated for each video item in each set. For the first set of video items, multiple groups are generated. The first set of video items may have a relatively little amount of metadata information for them. Each video item in the first set is assigned to one of the groups. Then, for each video item in the second set, one of the groups is selected based on embedding similarity. For each video item in the selected group, an embedding similarity is determined between that video item in the selected group and the video item in the second set. If the embedding similarity is above a certain threshold, then an association is generated for that pair of video items.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: A method for tracking financial transactions, including: obtaining a group of financial transactions; identifying a first financial transaction of the group of financial transactions involving a payment from a financial account held by a financial institution; allocating an amount of the first financial transaction corresponding to the payment to a budget category, wherein the first financial transaction includes a name of a merchant; accessing a website of the merchant; matching, on the website of the merchant, a list of purchased items to the first financial transaction based on the amount; extracting, after matching, the list of purchased items from the website of the merchant; identifying, after extracting the list of purchased items, a new budget category based on a purchased item of the list of purchased items; and reallocating at least a portion of the amount corresponding to the purchased item to the new budget category.

Abstract: Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.

Abstract: Systems, methods and articles of manufacture for dynamically injecting behaviors into view components are described herein. In an embodiment, a view component resides in an MXML file, while its behavior code (e.g., ACTIONSCRIPT) is stored in a separate file (e.g., .as file). In this way, the view component can be reused in separate applications where different behaviors may be applied to the same view component. In addition, because the behavior code is stored in a separate file, the behavior code is easier to read and maintain. Furthermore, behaviors can be dynamically (i.e., at runtime) injected into and un-injected from the view component. Embodiments of the invention also allow multiple behaviors to be injected into the same view component.

Abstract: Systems, methods and articles of manufacture for monitoring server cloud topology and resources are described herein. An embodiment includes determining a topological relationship of the computing nodes in the server cloud and constructing a data structure representing the topological relationship. The constructed data structure includes a plurality of node managed objects (MOs), where each node managed object corresponds to a computing node in the server cloud. The constructed data structure also includes a plurality of link managed objects, where each link managed object corresponds to inter-node communications between two or more computing nodes represented by the node managed objects. The node managed objects and the link managed objects publish events corresponding to changes affecting computing nodes in the server cloud.

Abstract: Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.

Abstract: Embodiments of the invention include apparatuses and methods relating to dual layer dielectric stacks for thick metal lines of microelectronic devices. In one embodiment, the dual layer dielectric stack includes a first dielectric layer that is planar and mechanically strong and the second dielectric layer can be patterned by photolithography to the required critical dimensions.

Abstract: An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a bond pad formed over the one or more metallization layers and electrically coupled to at least one of the metallization layers. A first passivation layer is formed over the bond pad and over the metallization layers and a redistribution interconnect formed on the passivation layer. A first via formed through the first passivation layer electrically couples the redistribution interconnect to the bond pad. A second passivation layer is formed on the redistribution interconnect to prevent thermomechanical degradation and improve electromigration performance. A dielectric layer is formed on the second passivation layer and a die-side bump is formed on the dielectric layer.

Abstract: Embodiments of the invention include apparatuses and methods relating to dual layer dielectric stacks for thick metal lines of microelectronic devices. In one embodiment, the dual layer dielectric stack includes a first dielectric layer that is planar and mechanically strong and the second dielectric layer can be patterned by photolithography to the required critical dimensions.