Patents by Inventor Subhash Mahajan
Subhash Mahajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9412580Abstract: Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.Type: GrantFiled: November 23, 2011Date of Patent: August 9, 2016Assignee: SOITECInventors: Chantal Arena, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Fanyu Meng
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Patent number: 9076666Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semi-conductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.Type: GrantFiled: November 23, 2011Date of Patent: July 7, 2015Assignees: SOITEC, Arizona Board of Regents For and On Behalf Arizona State UniversityInventors: Chantal Arena, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ilsu Han
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Patent number: 9012919Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.Type: GrantFiled: January 10, 2013Date of Patent: April 21, 2015Assignee: SoitecInventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
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Publication number: 20140217553Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.Type: ApplicationFiled: November 23, 2011Publication date: August 7, 2014Applicants: ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY, SoitecInventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow, Subhash Mahajan, Ilsu Han
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Patent number: 8574968Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.Type: GrantFiled: July 25, 2008Date of Patent: November 5, 2013Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State UniversityInventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
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Publication number: 20130234157Abstract: Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.Type: ApplicationFiled: November 23, 2011Publication date: September 12, 2013Applicant: SoitecInventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow, Subhash Mahajan, Fanyu Meng
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Publication number: 20130126896Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.Type: ApplicationFiled: January 10, 2013Publication date: May 23, 2013Applicant: SoitecInventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
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Patent number: 8377802Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.Type: GrantFiled: March 23, 2011Date of Patent: February 19, 2013Assignee: SoitecInventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
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Patent number: 8318612Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.Type: GrantFiled: November 14, 2008Date of Patent: November 27, 2012Assignees: Soitec, Arizona Board of Regents for and on behalf of Arizona State UniversityInventors: Chantal Arena, Subhash Mahajan
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Patent number: 8236593Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.Type: GrantFiled: May 14, 2008Date of Patent: August 7, 2012Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State UniversityInventors: Chantal Arena, Subhash Mahajan, Ilsu Han
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Publication number: 20110284863Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.Type: ApplicationFiled: March 23, 2011Publication date: November 24, 2011Applicants: Arizona Board of Regents for and on Behalf of Arizona State University, S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
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Publication number: 20110024747Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.Type: ApplicationFiled: November 14, 2008Publication date: February 3, 2011Applicant: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Chantal Arena, Subhash Mahajan
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Patent number: 7732306Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.Type: GrantFiled: July 25, 2008Date of Patent: June 8, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Chantal Arena, Subhash Mahajan, Ranjan Datta
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Publication number: 20100133548Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.Type: ApplicationFiled: May 14, 2008Publication date: June 3, 2010Inventors: Chantal Arena, Subhash Mahajan, Ilsu Han
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Publication number: 20090098343Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.Type: ApplicationFiled: July 25, 2008Publication date: April 16, 2009Inventors: Chantal ARENA, Christiaan J. Werkhoven, Ronald Thomas Bertram, JR., Ed Lidow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
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Publication number: 20090091002Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.Type: ApplicationFiled: July 25, 2008Publication date: April 9, 2009Inventors: Chantal ARENA, Subhash Mahajan, Ranjan Datta
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Patent number: 4620854Abstract: In the liquid phase epitaxy growth of Group III-V compound semiconductors using boat-slider apparatus, melt-carry-over is essentially eliminated by prebaking the metallic solvent (e.g., In shot) in the boat to form ingots and then etching the ingots in dilute nitric or hydrochloric acid prior to adding solutes (e.g., GaAs, InP, dopants). This process removes contaminants which coalesce on the ingots and cause poor wipe-off.Type: GrantFiled: October 21, 1985Date of Patent: November 4, 1986Assignee: AT&T Bell LaboratoriesInventors: Daniel Brasen, Michael A. DiGiuseppe, Jose A. Lourenco, Subhash Mahajan
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Patent number: 4566934Abstract: In the liquid phase epitaxy growth of Group III-V compound semiconductors using boat-slider apparatus, melt-carry-over is essentially eliminated by prebaking the metallic solvent (e.g., In shot) in the boat to form ingots and then etching the ingots in dilute nitric or hydrochloric acid prior to adding solutes (e.g., GaAs, InP, dopants). This process removes contaminants which coalesce on the ingots and cause poor wipe-off.Type: GrantFiled: October 28, 1982Date of Patent: January 28, 1986Assignee: AT&T Bell LaboratoriesInventors: Daniel Brasen, Michael A. DiGiuseppe, Jose A. Lourenco, Subhash Mahajan